From patchwork Thu Jan 28 10:21:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 8148451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 19F17BEEE5 for ; Thu, 28 Jan 2016 10:23:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4E99320218 for ; Thu, 28 Jan 2016 10:23:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6D0B92035B for ; Thu, 28 Jan 2016 10:23:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0DC4A6E7EB; Thu, 28 Jan 2016 02:23:56 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 803456E7EB for ; Thu, 28 Jan 2016 02:23:52 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 28 Jan 2016 02:23:53 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,358,1449561600"; d="scan'208";a="870587751" Received: from dev-inno.bj.intel.com ([10.238.135.69]) by orsmga001.jf.intel.com with ESMTP; 28 Jan 2016 02:23:49 -0800 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org Date: Thu, 28 Jan 2016 18:21:26 +0800 Message-Id: <1453976511-27322-5-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1453976511-27322-1-git-send-email-zhi.a.wang@intel.com> References: <1453976511-27322-1-git-send-email-zhi.a.wang@intel.com> Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com Subject: [Intel-gfx] [RFC 04/29] drm/i915: Ondemand populate context addressing mode bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As GVT-g workload scheduler may submit workloads from different VMs to i915, some VM may use 32bit PPGTT addressing mode, while some VMs may use 48bit addressing mode, the context addressing mode bit in the context descriptor has to be aligned with guest workload. If the to-be-submitted context is a GVT context. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/intel_lrc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index da97bc5..48e8ca2 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -302,7 +302,8 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *ring) * which remains valid until the context is unpinned. * * This is what a descriptor looks like, from LSB to MSB: - * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) + * bits 0-2,3-11: flags, GEN8_CTX_* (cached in ctx_desc_template) + * bits 3: Context addressing mode * bits 12-31: LRCA, GTT address of (the HWSP of) this context * bits 32-51: ctx ID, a globally unique tag (the LRCA again!) * bits 52-63: reserved, may encode the engine ID (for GuC) @@ -317,6 +318,13 @@ intel_lr_context_descriptor_update(struct intel_context *ctx, LRC_PPHWSP_PN * PAGE_SIZE; desc = ring->ctx_desc_template; /* bits 0-11 */ + + if (!ctx->gvt_context) + desc |= GEN8_CTX_ADDRESSING_MODE(dev) << /* bit 3 */ + GEN8_CTX_ADDRESSING_MODE_SHIFT; + else + desc |= ctx->gvt_context_addressing_mode[ring->id]; + desc |= lrca; /* bits 12-31 */ desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */