From patchwork Tue Feb 2 17:54:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 8192691 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 137F6BEEE5 for ; Tue, 2 Feb 2016 18:03:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 224AD202E9 for ; Tue, 2 Feb 2016 18:03:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D0ABC202EB for ; Tue, 2 Feb 2016 18:03:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0741D6E2E4; Tue, 2 Feb 2016 10:03:16 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 23AA96E2E4 for ; Tue, 2 Feb 2016 10:03:14 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP; 02 Feb 2016 10:02:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,385,1449561600"; d="scan'208";a="41172281" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by fmsmga004.fm.intel.com with ESMTP; 02 Feb 2016 10:02:01 -0800 From: Ramalingam C To: intel-gfx@lists.freedesktop.org Date: Tue, 2 Feb 2016 23:24:16 +0530 Message-Id: <1454435657-29027-1-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 Cc: jani.nikula@intel.com Subject: [Intel-gfx] [PATCH 1/2] drm/i915/BXT: Fixed COS blanking issue X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Uma Shankar During Charging OS mode, mipi display was blanking.This is because during driver load, though encoder, connector were active but crtc returned inactive. This caused sanitize function to disable the DSI panel. In AOS, this is fine since HWC will do a modeset and crtc, connector, encoder mapping will be restored. But in COS, no modeset is called, it just calls DPMS ON/OFF. This is fine on BYT/CHT since transcoder is common b/w all encoders. But for BXT, there is a separate mipi transcoder. Hence this needs special handling for BXT. Signed-off-by: Uma Shankar Signed-off-by: Ramalingam C --- drivers/gpu/drm/i915/intel_display.c | 107 ++++++++++++++++++++++++++++++++-- 1 file changed, 101 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a66220a..f8685f5 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7814,6 +7814,69 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) (intel_crtc->config->pipe_src_h - 1)); } +static void intel_get_dsi_pipe_timings(struct intel_crtc *crtc, + struct intel_crtc_state *pipe_config) +{ + struct drm_device *dev = crtc->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; + struct intel_encoder *encoder; + uint32_t tmp; + + tmp = I915_READ(HTOTAL(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_htotal = + ((tmp >> 16) & 0xffff) + 1; + tmp = I915_READ(HBLANK(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_hblank_end = + ((tmp >> 16) & 0xffff) + 1; + tmp = I915_READ(HSYNC(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_hsync_end = + ((tmp >> 16) & 0xffff) + 1; + + tmp = I915_READ(VBLANK(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_vblank_end = + ((tmp >> 16) & 0xffff) + 1; + tmp = I915_READ(VSYNC(cpu_transcoder)); + pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; + pipe_config->base.adjusted_mode.crtc_vsync_end = + ((tmp >> 16) & 0xffff) + 1; + + if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { + pipe_config->base.adjusted_mode.flags |= + DRM_MODE_FLAG_INTERLACE; + pipe_config->base.adjusted_mode.crtc_vtotal += 1; + pipe_config->base.adjusted_mode.crtc_vblank_end += 1; + } + + + for_each_encoder_on_crtc(dev, &crtc->base, encoder) { + struct intel_dsi *intel_dsi = + enc_to_intel_dsi(&encoder->base); + enum port port; + + pipe_config->pipe_bpp = intel_dsi->dsi_bpp; + for_each_dsi_port(port, intel_dsi->ports) { + pipe_config->base.adjusted_mode.crtc_hdisplay = + I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); + pipe_config->base.adjusted_mode.crtc_vdisplay = + I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); + pipe_config->base.adjusted_mode.crtc_vtotal = + I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); + } + } + + tmp = I915_READ(PIPESRC(crtc->pipe)); + pipe_config->pipe_src_h = (tmp & 0xffff) + 1; + pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; + + pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; + pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; +} + static void intel_get_pipe_timings(struct intel_crtc *crtc, struct intel_crtc_state *pipe_config) { @@ -9969,6 +10032,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; enum intel_display_power_domain pfit_domain; uint32_t tmp; + bool is_dsi = false; if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(crtc->pipe))) @@ -9999,17 +10063,48 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->cpu_transcoder = TRANSCODER_EDP; } + if (dev_priv->vbt.has_mipi) { + enum port port_num = (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) + ? PORT_A : PORT_C; + uint32_t dsi_ctrl = I915_READ(MIPI_CTRL(port_num)); + + tmp = I915_READ(BXT_MIPI_PORT_CTRL(port_num)); + if (tmp & DPI_ENABLE) { + enum pipe trans_dsi_pipe; + + switch (dsi_ctrl & BXT_PIPE_SELECT_MASK) { + default: + WARN(1, "unknown pipe linked to dsi transcoder\n"); + return false; + case BXT_PIPE_SELECT_A: + trans_dsi_pipe = PIPE_A; + break; + case BXT_PIPE_SELECT_B: + trans_dsi_pipe = PIPE_B; + break; + case BXT_PIPE_SELECT_C: + trans_dsi_pipe = PIPE_C; + break; + } + + if (trans_dsi_pipe == crtc->pipe) + is_dsi = true; + } + } + if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) return false; - tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); - if (!(tmp & PIPECONF_ENABLE)) - return false; - - haswell_get_ddi_port_state(crtc, pipe_config); + if (!is_dsi) { + tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); + if (!(tmp & PIPECONF_ENABLE)) + return false; - intel_get_pipe_timings(crtc, pipe_config); + haswell_get_ddi_port_state(crtc, pipe_config); + intel_get_pipe_timings(crtc, pipe_config); + } else + intel_get_dsi_pipe_timings(crtc, pipe_config); if (INTEL_INFO(dev)->gen >= 9) { skl_init_scalers(dev, crtc, pipe_config);