From patchwork Fri Feb 12 13:09:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhangi Shrivastava X-Patchwork-Id: 8290781 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9AD97BEEE5 for ; Fri, 12 Feb 2016 13:06:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9B10B203ED for ; Fri, 12 Feb 2016 13:06:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 96437203F4 for ; Fri, 12 Feb 2016 13:06:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A1716EAA0; Fri, 12 Feb 2016 05:06:49 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 833236EAA0 for ; Fri, 12 Feb 2016 05:06:46 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 12 Feb 2016 05:06:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,435,1449561600"; d="scan'208";a="910716921" Received: from shubhangi-desktop.iind.intel.com ([10.223.25.115]) by orsmga002.jf.intel.com with ESMTP; 12 Feb 2016 05:06:34 -0800 From: Shubhangi Shrivastava To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Feb 2016 18:39:44 +0530 Message-Id: <1455282584-6350-2-git-send-email-shubhangi.shrivastava@intel.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1455282584-6350-1-git-send-email-shubhangi.shrivastava@intel.com> References: <1455282584-6350-1-git-send-email-shubhangi.shrivastava@intel.com> Cc: Shubhangi Shrivastava Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Set invert bit for hpd based on VBT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sets the invert bit for hpd detection for each port based on VBT configuration. Since each AOB can be designed to depend on invert bit or not, it is expected if an AOB requires invert bit, the user will set respective bit in VBT. v2: Separated VBT parsing from the rest of the logic. (Jani) Signed-off-by: Sivakumar Thulasimani Signed-off-by: Durgadoss R Signed-off-by: Shubhangi Shrivastava --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_irq.c | 43 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 9 ++++++++ drivers/gpu/drm/i915/intel_bios.c | 42 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 95 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8216665..457f175 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3393,6 +3393,7 @@ extern void intel_i2c_reset(struct drm_device *dev); /* intel_bios.c */ int intel_bios_init(struct drm_i915_private *dev_priv); bool intel_bios_is_valid_vbt(const void *buf, size_t size); +bool intel_bios_is_port_hpd_inverted(struct drm_device *dev, enum port port); /* intel_opregion.c */ #ifdef CONFIG_ACPI diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 25a8937..fb95fb0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -36,6 +36,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include "intel_drv.h" +#include "intel_bios.h" /** * DOC: interrupt handling @@ -3424,6 +3425,47 @@ static void ibx_hpd_irq_setup(struct drm_device *dev) I915_WRITE(PCH_PORT_HOTPLUG, hotplug); } +/* + * For BXT invert bit has to be set based on AOB design + * for HPD detection logic, update it based on VBT fields. + */ +static void bxt_hpd_set_invert(struct drm_device *dev, u32 hotplug_port) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int reg_val, val = 0; + enum port port; + + for (port = PORT_A; port <= PORT_C; port++) { + + /* Proceed only if invert bit is set */ + if (intel_bios_is_port_hpd_inverted(dev, port)) { + switch (port) { + case PORT_A: + if (hotplug_port & BXT_DE_PORT_HP_DDIA) + val |= BXT_DDIA_HPD_INVERT; + break; + case PORT_B: + if (hotplug_port & BXT_DE_PORT_HP_DDIB) + val |= BXT_DDIB_HPD_INVERT; + break; + case PORT_C: + if (hotplug_port & BXT_DE_PORT_HP_DDIC) + val |= BXT_DDIC_HPD_INVERT; + break; + default: + DRM_ERROR("HPD invert set for invalid port %d\n", + port); + break; + } + } + } + reg_val = I915_READ(BXT_HOTPLUG_CTL); + DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x val:%x\n", + reg_val, hotplug_port, val); + reg_val &= ~BXT_DDI_HPD_INVERT_MASK; + I915_WRITE(BXT_HOTPLUG_CTL, reg_val | val); +} + static void spt_hpd_irq_setup(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -3494,6 +3536,7 @@ static void bxt_hpd_irq_setup(struct drm_device *dev) hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; I915_WRITE(PCH_PORT_HOTPLUG, hotplug); + bxt_hpd_set_invert(dev, enabled_irqs); } static void ibx_irq_postinstall(struct drm_device *dev) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6732fc1..66cf92e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5940,6 +5940,15 @@ enum skl_disp_power_wells { #define GEN8_PCU_IIR _MMIO(0x444e8) #define GEN8_PCU_IER _MMIO(0x444ec) +/* BXT hotplug control */ +#define BXT_HOTPLUG_CTL _MMIO(0xC4030) +#define BXT_DDIA_HPD_INVERT (1 << 27) +#define BXT_DDIC_HPD_INVERT (1 << 11) +#define BXT_DDIB_HPD_INVERT (1 << 3) +#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \ + BXT_DDIB_HPD_INVERT | \ + BXT_DDIC_HPD_INVERT) + #define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004) /* Required on all Ironlake and Sandybridge according to the B-Spec. */ #define ILK_ELPIN_409_SELECT (1 << 25) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index a26d4b4..24d0077 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -105,6 +105,48 @@ find_section(const void *_bdb, int section_id) return NULL; } +bool +intel_bios_is_port_hpd_inverted(struct drm_device *dev, enum port port) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int i; + + if (!IS_BROXTON(dev)) { + DRM_ERROR("Bit inversion is not required in this platform\n"); + return false; + } + + for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { + + if (dev_priv->vbt.child_dev[i].common.hpd_invert == 1) { + + switch (dev_priv->vbt.child_dev[i].common.dvo_port) { + case DVO_PORT_DPA: + case DVO_PORT_HDMIA: + if (port == PORT_A) + return true; + break; + case DVO_PORT_DPB: + case DVO_PORT_HDMIB: + if (port == PORT_B) + return true; + break; + case DVO_PORT_DPC: + case DVO_PORT_HDMIC: + if (port == PORT_C) + return true; + break; + default: + DRM_DEBUG_KMS("This dvo port %d doesn't need invert\n", + dev_priv->vbt.child_dev[i].common.dvo_port); + break; + } + } + } + + return false; +} + static void fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, const struct lvds_dvo_timing *dvo_timing)