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[02/11] drm/i915: Constrain intel_context::global_id to 20 bits

Message ID 1455600439-18480-3-git-send-email-sourab.gupta@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sourab.gupta@intel.com Feb. 16, 2016, 5:27 a.m. UTC 
From: Robert Bragg <robert@sixbynine.org>

This will allow the ID to be given to the HW as the unique context
identifier that's written, for example, to the context status buffer
on preemption and included in reports written by the OA unit.

Cc: Sourab Gupta <sourab.gupta@intel.com>
Signed-off-by: Robert Bragg <robert@sixbynine.org>
---
 drivers/gpu/drm/i915/i915_gem_context.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 6f38810..3a90e79 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -90,6 +90,10 @@ 
 #include "i915_drv.h"
 #include "i915_trace.h"
 
+/* With execlist scheduling we can program our own HW context ID but we we
+ * are limited to 20bits */
+#define I915_MAX_HW_CTX_ID ((1<<20)-1)
+
 /* This is a HW constraint. The value below is the largest known requirement
  * I've seen in a spec to date, and that was a workaround for a non-shipping
  * part. It should be safe to decrease this, but it's more future proof as is.
@@ -257,13 +261,8 @@  __create_hw_context(struct drm_device *dev,
 	ctx->file_priv = file_priv;
 	ctx->user_handle = ret;
 
-	/* TODO: If required, this global id can be used for programming the hw
-	 * fields too. In that case, we'll have take care of hw restrictions
-	 * while allocating idr. e.g. for some hw, we may not have full 32 bits
-	 * available.
-	 */
 	ret = idr_alloc_cyclic(&dev_priv->global_ctx_idr,
-				ctx, 0, 0, GFP_KERNEL);
+				ctx, 0, I915_MAX_HW_CTX_ID, GFP_KERNEL);
 	if (ret < 0)
 		goto err_out;