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[libdrm] intel/skl: Add missing SKL PCI IDs

Message ID 1455705619-29902-1-git-send-email-michal.winiarski@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Michał Winiarski Feb. 17, 2016, 10:40 a.m. UTC 
Used by production devices:
    Intel(R) HD Graphics 510
    Intel(R) HD Graphics 535
    Intel(R) Iris(TM) Graphics 550
    Intel(R) Iris(TM) Graphics P555

Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com>
---
 intel/intel_chipset.h | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

Comments

Lionel Landwerlin Feb. 22, 2016, 5:48 p.m. UTC | #1 
On 17/02/16 10:40, Micha? Winiarski wrote:
> Used by production devices:
>      Intel(R) HD Graphics 510
>      Intel(R) HD Graphics 535
>      Intel(R) Iris(TM) Graphics 550
>      Intel(R) Iris(TM) Graphics P555
>
> Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com>
>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin Feb. 22, 2016, 5:49 p.m. UTC | #2 
On 17/02/16 10:40, Micha? Winiarski wrote:
> Used by production devices:
>      Intel(R) HD Graphics 510
>      Intel(R) HD Graphics 535
>      Intel(R) Iris(TM) Graphics 550
>      Intel(R) Iris(TM) Graphics P555
>
> Signed-off-by: Micha? Winiarski <michal.winiarski@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
diff mbox

Patch

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 35148e5..f52e149 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -168,6 +168,7 @@ 
 #define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
 #define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
 #define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A /* Reserved */
+#define PCI_CHIP_SKYLAKE_H_GT1		0x190B
 #define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E /* Reserved */
 #define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
 #define PCI_CHIP_SKYLAKE_FUSED0_GT2	0x1913 /* Reserved */
@@ -179,9 +180,12 @@ 
 #define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
 #define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
 #define PCI_CHIP_SKYLAKE_MOBILE_GT2	0x1921 /* Reserved */
-#define PCI_CHIP_SKYLAKE_GT3		0x1926
-#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B /* Reserved */
+#define PCI_CHIP_SKYLAKE_ULT_GT3_0	0x1923
+#define PCI_CHIP_SKYLAKE_ULT_GT3_1	0x1926
+#define PCI_CHIP_SKYLAKE_ULT_GT3_2	0x1927
 #define PCI_CHIP_SKYLAKE_SRV_GT4	0x192A
+#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B /* Reserved */
+#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192D
 #define PCI_CHIP_SKYLAKE_DT_GT4		0x1932
 #define PCI_CHIP_SKYLAKE_SRV_GT4X	0x193A
 #define PCI_CHIP_SKYLAKE_H_GT4		0x193B
@@ -373,10 +377,11 @@ 
 #define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
 				 IS_CHERRYVIEW(devid))
 
-#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
+#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_H_GT1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
 
 #define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2	|| \
@@ -389,8 +394,11 @@ 
 				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
 
-#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_GT3	|| \
-				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3)
+#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
+				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
 
 #define IS_SKL_GT4(devid)	((devid) == PCI_CHIP_SKYLAKE_SRV_GT4	|| \
 				 (devid) == PCI_CHIP_SKYLAKE_DT_GT4	|| \