From patchwork Thu Feb 18 11:42:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 8349181 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A5D27C0553 for ; Thu, 18 Feb 2016 11:45:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A4AF3202FE for ; Thu, 18 Feb 2016 11:45:31 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BD1922022A for ; Thu, 18 Feb 2016 11:45:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E6306EB69; Thu, 18 Feb 2016 11:45:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 0DA4E6EB69 for ; Thu, 18 Feb 2016 11:45:27 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 18 Feb 2016 03:45:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,465,1449561600"; d="scan'208";a="654960168" Received: from dev-inno.bj.intel.com ([10.238.135.69]) by FMSMGA003.fm.intel.com with ESMTP; 18 Feb 2016 03:45:25 -0800 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org Date: Thu, 18 Feb 2016 19:42:21 +0800 Message-Id: <1455795741-3487-15-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455795741-3487-1-git-send-email-zhi.a.wang@intel.com> References: <1455795741-3487-1-git-send-email-zhi.a.wang@intel.com> Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com, zhiyuan.lv@intel.com Subject: [Intel-gfx] [RFCv2 14/14] drm/i915: Introduce GVT context creation API X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP GVT workload scheduler needs special host LRC contexts, the so called "shadow LRC context" to submit guest workload to host i915. During the guest workload submission, GVT fills the shadow LRC context with the content of guest LRC context: engine context is copied without changes, ring context is mostly owned by host i915. The GVT-g workload scheduler flow: +-----------+ +-----------+ | GVT Guest | | GVT Guest | +-+-----^---+ +-+-----^---+ | | | | | | GVT-g | | GVT-g vELSP write| | emulates vELSP write| | emulates | | Execlist/CSB | | Execlist/CSB | | Status | | Status | | | | +------v-----+-------------------------v-----+---------+ | GVT Virtual Execlist Submission | +------+-------------------------------+---------------+ | | | Per-VM/Ring Workoad Q | Per-VM/Ring Workload Q +---------------------+--+ +------------------------+ +---v--------+ ^ +---v--------+ |GVT Workload|... | |GVT Workload|... +------------+ | +------------+ | | Pick Workload from Q +--------------------+---------------------------------+ | GVT Workload Scheduler | +--------------------+---------------------------------+ | * Shadow guest LRC context +------v------+ * Shadow guest ring buffer | GVT Context | * Scan/Patch guest RB instructions +------+------+ | v Host i915 GEM Submission v2: Mostly based on Daniel's idea. Call the refactored core logic of GEM context creation service and LRC context creation service to create the GVT context. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 52 +++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0850b35..fa31680 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3278,6 +3278,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); void i915_gem_context_free(struct kref *ctx_ref); struct drm_i915_gem_object * i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); +struct intel_context *i915_gem_create_gvt_context(struct drm_device *dev); static inline void i915_gem_context_reference(struct intel_context *ctx) { kref_get(&ctx->ref); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index cda09f7..65f78c6 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -369,6 +369,58 @@ i915_gem_create_context(struct drm_device *dev, return ctx; } +/** + * i915_i915_gem_create_gvt_context - create a GVT GEM context + * @dev: drm device * + * + * This function is used to create a GVT specific GEM context. + * + * Returns: + * pointer to intel_context on success, NULL if failed + * + */ +struct intel_context * +i915_gem_create_gvt_context(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct i915_gem_context_create_params params; + struct intel_lr_context_alloc_params alloc_params; + struct intel_context *ctx; + int i, ret; + + memset(¶ms, 0, sizeof(params)); + memset(&alloc_params, 0, sizeof(params)); + + params.file_priv = NULL; + params.has_legacy_ctx = false; + params.has_ppgtt = false; + params.is_default_ctx = false; + + alloc_params.ctx_needs_init = false; + alloc_params.ctx_needs_status_change_notification = true; + alloc_params.ctx_needs_single_submission = true; + alloc_params.ringbuffer_size = 512 * PAGE_SIZE; + + mutex_lock(&dev->struct_mutex); + + ctx = __i915_gem_create_context(dev, ¶ms); + if (IS_ERR(ctx)) + return ctx; + + for (i = 0; i < I915_NUM_RINGS; i++) { + alloc_params.ring = &dev_priv->ring[i]; + ret = __intel_lr_context_deferred_alloc(ctx, &alloc_params); + if (ret) { + i915_gem_context_unreference(ctx); + ctx = NULL; + goto out; + } + } +out: + mutex_unlock(&dev->struct_mutex); + return ctx; +} + static void i915_gem_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine) {