From patchwork Thu Feb 18 11:42:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 8349091 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AFE3A9F399 for ; Thu, 18 Feb 2016 11:45:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D06692022A for ; Thu, 18 Feb 2016 11:45:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8423020386 for ; Thu, 18 Feb 2016 11:45:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D685D6EB67; Thu, 18 Feb 2016 11:44:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id D7B896EB67 for ; Thu, 18 Feb 2016 11:44:57 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP; 18 Feb 2016 03:44:57 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,465,1449561600"; d="scan'208";a="654959712" Received: from dev-inno.bj.intel.com ([10.238.135.69]) by FMSMGA003.fm.intel.com with ESMTP; 18 Feb 2016 03:44:56 -0800 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org Date: Thu, 18 Feb 2016 19:42:11 +0800 Message-Id: <1455795741-3487-5-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455795741-3487-1-git-send-email-zhi.a.wang@intel.com> References: <1455795741-3487-1-git-send-email-zhi.a.wang@intel.com> Cc: daniel.vetter@ffwll.ch, david.j.cowperthwaite@intel.com, zhiyuan.lv@intel.com Subject: [Intel-gfx] [RFCv2 04/14] drm/i915: factor out alloc_context_idr() and __i915_gem_create_context() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For flexible GEM context creation, we factor out __i915_gem_create_context as the core logic of creation a GEM context. After the refactor, it more likesa context creation servcie, which is able to create context by explicit requirement of upper level components, not by the assumptions of incoming parameters. For the assumptions in original implementation, we keep them in the upper level wrapper: i915_gem_create_context(). alloc_context_idr() is another function factored out to setup a IDR for ordinary GEM context. Some context, e.g. GVT context, maybe more than one kernel context in furture (currently there is only one kernel context: the default context) doesn't need a IDR. So we make it an option in context creation. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_context.c | 62 ++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 4be2ce9..38e9fe1 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -235,17 +235,7 @@ __create_hw_context(struct drm_device *dev, ctx->legacy_hw_ctx.rcs_state = obj; } - /* Default context will never have a file_priv */ - if (file_priv != NULL) { - ret = idr_alloc(&file_priv->context_idr, ctx, - DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); - if (ret < 0) - goto err_out; - } else - ret = DEFAULT_CONTEXT_HANDLE; - ctx->file_priv = file_priv; - ctx->user_handle = ret; /* NB: Mark all slices as needing a remap so that when the context first * loads it will restore whatever remap state already exists. If there * is no remap info, it will be a NOP. */ @@ -260,13 +250,8 @@ err_out: return ERR_PTR(ret); } -/** - * The default context needs to exist per ring that uses contexts. It stores the - * context state of the GPU for applications that don't utilize HW contexts, as - * well as an idle case. - */ static struct intel_context * -i915_gem_create_context(struct drm_device *dev, +__i915_gem_create_context(struct drm_device *dev, struct drm_i915_file_private *file_priv) { const bool is_global_default_ctx = file_priv == NULL; @@ -316,11 +301,54 @@ err_unpin: if (is_global_default_ctx && ctx->legacy_hw_ctx.rcs_state) i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); err_destroy: - idr_remove(&file_priv->context_idr, ctx->user_handle); i915_gem_context_unreference(ctx); return ERR_PTR(ret); } +static inline int alloc_context_idr(struct drm_device *dev, + struct intel_context *ctx) +{ + int ret; + + /* Default context will never have a file_priv */ + if (ctx->file_priv != NULL) { + ret = idr_alloc(&ctx->file_priv->context_idr, ctx, + DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL); + if (ret < 0) + return ret; + } else { + ret = DEFAULT_CONTEXT_HANDLE; + } + + ctx->user_handle = ret; + return 0; +} + +/** + * The default context needs to exist per ring that uses contexts. It stores the + * context state of the GPU for applications that don't utilize HW contexts, as + * well as an idle case. + */ +static struct intel_context * +i915_gem_create_context(struct drm_device *dev, + struct drm_i915_file_private *file_priv) +{ + struct intel_context *ctx; + int ret; + + ctx = __i915_gem_create_context(dev, file_priv); + if (IS_ERR(ctx)) + return ctx; + + ret = alloc_context_idr(dev, ctx); + if (ret < 0) { + i915_gem_context_unreference(ctx); + return ERR_PTR(ret); + } + + return ctx; +} + static void i915_gem_context_unpin(struct intel_context *ctx, struct intel_engine_cs *engine) {