| Message ID | 1455893892-25406-1-git-send-email-michel.thierry@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 19/02/2016 14:58, Michel Thierry wrote: > The cache line offset for the Indirect CS context (0x21C8) varies from gen > to gen. > > v2: Move it into a function (Arun), use MISSING_CASE (Chris) > > Cc: Arun Siluvery <arun.siluvery@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Signed-off-by: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 5c0bf02..b1f2886 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -226,7 +226,8 @@ enum { > FAULT_AND_CONTINUE /* Unsupported */ > }; > #define GEN8_CTX_ID_SHIFT 32 > -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 > +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 > +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 > > static int intel_lr_context_pin(struct drm_i915_gem_request *rq); > static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, > @@ -2264,6 +2265,27 @@ make_rpcs(struct drm_device *dev) > return rpcs; > } > > +static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring) > +{ > + u32 indirect_ctx_offset; > + > + switch (INTEL_INFO(ring->dev)->gen) { > + default: > + MISSING_CASE(INTEL_INFO(ring->dev)->gen); > + /* fall through */ > + case 9: > + indirect_ctx_offset = > + GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; > + break; > + case 8: > + indirect_ctx_offset = > + GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; > + break; > + } > + > + return indirect_ctx_offset; > +} > + > static int > populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, > struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) > @@ -2336,7 +2358,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o > (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); > > reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = > - CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; > + intel_lr_indirect_ctx_offset(ring) << 6; > > reg_state[CTX_BB_PER_CTX_PTR+1] = > (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | > Agrees with spec, looks good to me, Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> regards Arun
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5c0bf02..b1f2886 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -226,7 +226,8 @@ enum { FAULT_AND_CONTINUE /* Unsupported */ }; #define GEN8_CTX_ID_SHIFT 32 -#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 +#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 +#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 static int intel_lr_context_pin(struct drm_i915_gem_request *rq); static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, @@ -2264,6 +2265,27 @@ make_rpcs(struct drm_device *dev) return rpcs; } +static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring) +{ + u32 indirect_ctx_offset; + + switch (INTEL_INFO(ring->dev)->gen) { + default: + MISSING_CASE(INTEL_INFO(ring->dev)->gen); + /* fall through */ + case 9: + indirect_ctx_offset = + GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + case 8: + indirect_ctx_offset = + GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; + break; + } + + return indirect_ctx_offset; +} + static int populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) @@ -2336,7 +2358,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = - CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; + intel_lr_indirect_ctx_offset(ring) << 6; reg_state[CTX_BB_PER_CTX_PTR+1] = (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
The cache line offset for the Indirect CS context (0x21C8) varies from gen to gen. v2: Move it into a function (Arun), use MISSING_CASE (Chris) Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-)