From patchwork Mon Feb 22 02:23:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 8370331 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9EDCF9F88A for ; Mon, 22 Feb 2016 02:33:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9BF6720375 for ; Mon, 22 Feb 2016 02:33:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6B2982034C for ; Mon, 22 Feb 2016 02:33:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2FD266E061; Mon, 22 Feb 2016 02:33:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org X-Greylist: delayed 550 seconds by postgrey-1.35 at gabe; Mon, 22 Feb 2016 02:33:21 UTC Received: from mail.bwidawsk.net (zangief.bwidawsk.net [107.170.211.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id F19786E046 for ; Mon, 22 Feb 2016 02:33:21 +0000 (UTC) Received: by mail.bwidawsk.net (Postfix, from userid 5001) id E75C9122A5E; Sun, 21 Feb 2016 18:24:11 -0800 (PST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-ASN: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from gibson.kumite (67-5-174-85.ptld.qwest.net [67.5.174.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client did not present a certificate) by mail.bwidawsk.net (Postfix) with ESMTPSA id B241512254F; Sun, 21 Feb 2016 18:24:03 -0800 (PST) From: Ben Widawsky To: Intel GFX Date: Sun, 21 Feb 2016 18:23:57 -0800 Message-Id: <1456107838-2265-1-git-send-email-ben@bwidawsk.net> X-Mailer: git-send-email 2.7.1 Cc: Ben Widawsky Subject: [Intel-gfx] [PATCH 1/2] intel_gpu_top: Skip head/tail reads on HSW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Haswell has a known issue when doing concurrent reads of MMIO (see reference for details). This issue results in a system wide unrecoverable hang. As this tool is shipped by default in the IGT package, this is a very mean behavior to accidentally impose on the user. This patch shuts this behavior down by default on HSW, and prints a warning. An upcoming patch will provide an override for the insane. References: https://lists.freedesktop.org/archives/mesa-dev/2013-July/041692.html Signed-off-by: Ben Widawsky --- man/intel_gpu_top.man | 2 ++ tools/intel_gpu_top.c | 28 +++++++++++++++++++++++----- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/man/intel_gpu_top.man b/man/intel_gpu_top.man index b307a23..d90a7ee 100644 --- a/man/intel_gpu_top.man +++ b/man/intel_gpu_top.man @@ -39,3 +39,5 @@ header. .SH BUGS Some GPUs report some units as busy when they aren't, such that even when idle and not hung, it will show up as 100% busy. +.TP +Haswell GPU may hang when trying to determine ring busyness, and so it is disabled by default. diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c index 4f327c6..33a8e0c 100644 --- a/tools/intel_gpu_top.c +++ b/tools/intel_gpu_top.c @@ -316,6 +316,7 @@ struct ring { int head, tail, size; uint64_t full; int idle; + bool skip_ring_reads; }; static uint32_t ring_read(struct ring *ring, uint32_t reg) @@ -323,9 +324,14 @@ static uint32_t ring_read(struct ring *ring, uint32_t reg) return INREG(ring->mmio + reg); } -static void ring_init(struct ring *ring) +static void ring_init(struct ring *ring, uint32_t devid) { ring->size = (((ring_read(ring, RING_LEN) & RING_NR_PAGES) >> 12) + 1) * 4096; + + if (IS_HASWELL(devid)) { + fprintf(stderr, "Skipping reads of head, and tail registers to avoid hangs\n"); + ring->skip_ring_reads = true; + } } static void ring_reset(struct ring *ring) @@ -340,6 +346,9 @@ static void ring_sample(struct ring *ring) if (!ring->size) return; + if (ring->skip_ring_reads) + return; + ring->head = ring_read(ring, RING_HEAD) & HEAD_ADDR; ring->tail = ring_read(ring, RING_TAIL) & TAIL_ADDR; @@ -366,6 +375,15 @@ static void ring_print(struct ring *ring, unsigned long samples_per_sec) if (!ring->size) return; + if (ring->skip_ring_reads) { + len = printf("%25s busy: ??%%: ", ring->name); + print_percentage_bar(0, len); + printf("%24s space: ??\?/%d\n", + ring->name, + ring->size); + return; + } + percent_busy = 100 - 100 * ring->idle / samples_per_sec; len = printf("%25s busy: %3d%%: ", ring->name, percent_busy); @@ -513,12 +531,12 @@ int main(int argc, char **argv) /* Grab access to the registers */ intel_register_access_init(pci_dev, 0); - ring_init(&render_ring); + ring_init(&render_ring, devid); if (IS_GEN4(devid) || IS_GEN5(devid)) - ring_init(&bsd_ring); + ring_init(&bsd_ring, devid); if (IS_GEN6(devid) || IS_GEN7(devid)) { - ring_init(&bsd6_ring); - ring_init(&blt_ring); + ring_init(&bsd6_ring, devid); + ring_init(&blt_ring, devid); } /* Initialize GPU stats */