| Message ID | 1456418912-25723-3-git-send-email-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index a3fd699..6a53e4f 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -835,7 +835,8 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct intel_fbc *fbc = &dev_priv->fbc; bool enable_by_default = IS_HASWELL(dev_priv) || - IS_BROADWELL(dev_priv); + IS_BROADWELL(dev_priv) || + IS_SKYLAKE(dev_priv); if (intel_vgpu_active(dev_priv->dev)) { fbc->no_fbc_reason = "VGPU is active";
Now that we're more protected against user space doing frontbuffer mmap rendering, the last - how many times did I say this before? - SKL problem seems to be solved. So let's give it a try. If you reached this commit through git bisect or if you just want more information about FBC, please see: commit a98ee79317b4091cafb502b4ffdbbbe1335e298c Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Feb 16 18:47:21 2016 -0200 drm/i915/fbc: enable FBC by default on HSW and BDW Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_fbc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)