From patchwork Tue Mar 1 17:14:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 8467571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2CC73C0553 for ; Tue, 1 Mar 2016 17:14:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1E16D202FF for ; Tue, 1 Mar 2016 17:14:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 19E522014A for ; Tue, 1 Mar 2016 17:14:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C0806E6FC; Tue, 1 Mar 2016 17:14:54 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 582916E701 for ; Tue, 1 Mar 2016 17:14:52 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP; 01 Mar 2016 09:14:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,524,1449561600"; d="scan'208";a="924459171" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by orsmga002.jf.intel.com with ESMTP; 01 Mar 2016 09:14:49 -0800 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 1 Mar 2016 17:14:38 +0000 Message-Id: <1456852479-9375-2-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1456852479-9375-1-git-send-email-arun.siluvery@linux.intel.com> References: <1456852479-9375-1-git-send-email-arun.siluvery@linux.intel.com> Cc: Tomas Elf Subject: [Intel-gfx] [PATCH 1/2] drm/i915/tdr: Add helper function to perform Engine reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch only adds a function to reset an engine and it is in preparation for the complete engine reset feature. At the moment this is only made available from Gen8 onwards. v2: use indexed initialization and keep everything under forcewake (Dave) Cc: Dave Gordon Cc: Mika Kuoppala Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_uncore.c | 67 +++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 09b85b2..55dadfc 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2741,6 +2741,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); #endif extern int intel_gpu_reset(struct drm_device *dev); +extern int intel_engine_reset(struct intel_engine_cs *engine); extern bool intel_has_gpu_reset(struct drm_device *dev); extern int i915_reset(struct drm_device *dev); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f76cbf3..a798e40 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -164,6 +164,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define GEN6_GRDOM_RENDER (1 << 1) #define GEN6_GRDOM_MEDIA (1 << 2) #define GEN6_GRDOM_BLT (1 << 3) +#define GEN6_GRDOM_VECS (1 << 4) +#define GEN8_GRDOM_MEDIA2 (1 << 7) #define RING_PP_DIR_BASE(ring) _MMIO((ring)->mmio_base+0x228) #define RING_PP_DIR_BASE_READ(ring) _MMIO((ring)->mmio_base+0x518) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 436d8f2..d003b78 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1616,6 +1616,73 @@ bool intel_has_gpu_reset(struct drm_device *dev) return intel_get_gpu_reset(dev) != NULL; } +static int wait_for_engine_reset(struct drm_i915_private *dev_priv, + unsigned int grdom) +{ + int ret; + +#define _CND ((__raw_i915_read32(dev_priv, GEN6_GDRST) & grdom) == 0) + + /* + * Spin waiting for the device to ack the reset request. + * Times out after 500 us + */ + ret = wait_for_atomic_us(_CND, 500); +#undef _CND + + return ret; +} + +static int gen8_do_engine_reset(struct intel_engine_cs *engine) +{ + struct drm_device *dev = engine->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 reset_ctl; + int ret; + int engine_mask[I915_NUM_RINGS] = { + [RCS] = GEN6_GRDOM_RENDER, + [BCS] = GEN6_GRDOM_BLT, + [VCS] = GEN6_GRDOM_MEDIA, + [VCS2] = GEN8_GRDOM_MEDIA2, + [VECS] = GEN6_GRDOM_VECS, + }; + + if (WARN_ON_ONCE(!intel_ring_initialized(engine))) + return -EINVAL; + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + /* reset engine */ + __raw_i915_write32(dev_priv, GEN6_GDRST, engine_mask[engine->id]); + + ret = wait_for_engine_reset(dev_priv, engine_mask[engine->id]); + if (ret) + goto out; + + /* Confirm that reset control register is back to normal after reset */ + reset_ctl = I915_READ(RING_RESET_CTL(engine->mmio_base)); + WARN((reset_ctl & (RESET_CTL_REQUEST_RESET | RESET_CTL_READY_TO_RESET)), + "%s reset control still active after reset !! (0x%08x)\n", + engine->name, reset_ctl); + +out: + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + return ret; +} + +int intel_engine_reset(struct intel_engine_cs *engine) +{ + struct drm_device *dev = engine->dev; + + if (INTEL_INFO(dev)->gen < 8) { + DRM_ERROR("Engine Reset not supported on Gen%d\n", + INTEL_INFO(dev)->gen); + return -EINVAL; + } + + return gen8_do_engine_reset(engine); +} + bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv) { return check_for_unclaimed_mmio(dev_priv);