From patchwork Tue Mar 8 11:38:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 8532571 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DB6829F2B4 for ; Tue, 8 Mar 2016 11:38:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 05230201C8 for ; Tue, 8 Mar 2016 11:38:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 231E7200ED for ; Tue, 8 Mar 2016 11:38:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A4956E01C; Tue, 8 Mar 2016 11:38:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 04A796E01C for ; Tue, 8 Mar 2016 11:38:25 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 08 Mar 2016 03:38:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,556,1449561600"; d="scan'208";a="904858117" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by orsmga001.jf.intel.com with ESMTP; 08 Mar 2016 03:38:24 -0800 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 8 Mar 2016 11:38:17 +0000 Message-Id: <1457437098-21689-2-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457437098-21689-1-git-send-email-arun.siluvery@linux.intel.com> References: <1457437098-21689-1-git-send-email-arun.siluvery@linux.intel.com> Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH v2 1/2] drm/i915: Add function to reset an engine domain X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Partial port of a patch from Mika that modifies reset function to handle per engine resets. A domain reset function is introduces which accepts a mask of all domains to be reset. In case of per engine reset only single engine domain is specified where as for legacy full gpu reset all engine domains are specified. This change also supports to reset GuC which is required for some of the WA where fw load can fail and we retry after resetting GuC. Cc: Mika Kuoppala Cc: Dave Gordon Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/intel_uncore.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index d31447f..80e38d5 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1510,6 +1510,21 @@ static int ironlake_do_reset(struct drm_device *dev) return 0; } +static int gen6_domain_reset(struct drm_i915_private *dev_priv, + u32 hw_domain_mask) +{ + int ret; + + __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask); + +#define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0) + /* Spin waiting for the device to ack the reset requests */ + ret = wait_for_atomic_us(ACKED, 500); +#undef ACKED + + return ret; +} + static int gen6_do_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private;