From patchwork Fri Mar 11 13:12:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramalingam C X-Patchwork-Id: 8565451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 839ECC0553 for ; Fri, 11 Mar 2016 13:23:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7342120259 for ; Fri, 11 Mar 2016 13:23:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C03CB20222 for ; Fri, 11 Mar 2016 13:23:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AFD336EABE; Fri, 11 Mar 2016 13:23:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id DFD316EABD for ; Fri, 11 Mar 2016 13:20:32 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 11 Mar 2016 05:20:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,320,1455004800"; d="scan'208";a="762333667" Received: from ramaling-desktop.iind.intel.com ([10.223.26.95]) by orsmga003.jf.intel.com with ESMTP; 11 Mar 2016 05:20:31 -0800 From: Ramalingam C To: intel-gfx@lists.freedesktop.org Date: Fri, 11 Mar 2016 18:42:05 +0530 Message-Id: <1457701925-15890-1-git-send-email-ramalingam.c@intel.com> X-Mailer: git-send-email 1.7.9.5 Cc: jani.nikula@intel.com, daniel.vetter@intel.com Subject: [Intel-gfx] [PATCH] drm/i915/BXT: Tolerance at BXT DSI pipe_config comparison X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP At BXT DSI, PIPE registers are inactive. So we can get the PIPE's mode parameters from them. The possible option is retriving them from the PORT registers. But mode timing parameters are progammed to port registers interms of byteclocks. The formula used to convert the pixels interms of byteclk is DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, 8 * 100), lane_count); So we retrieve them, interms of pixels as DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), (bpp * burst_mode_ratio)); Due to the multiple DIV_ROUND_UP in both formulas we get the worst case delta in the retrieved PIPE's timing parameter as below DIV_ROUND_UP((8 * intel_dsi->lane_count * 100), (dsi_pixel_format_bpp(intel_dsi->pixel_format) * intel_dsi->burst_mode_ratio))) This converson of byteclk to pixel is required for hsync, hfp and hbp. Which intern impacts horrizontal timing parameters. At worst case to get htotal all there parameters are added with hactive. Hence delta will be 3 times of above formula. Hence this value is considered as tolerance for pipe_config comparison, in case of BXT DSI. Signed-off-by: Ramalingam C This change is required for https://lists.freedesktop.org/archives/intel-gfx/2016-February/088653.html --- drivers/gpu/drm/i915/intel_display.c | 62 +++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7068dc1..46ce662 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12653,6 +12653,9 @@ intel_pipe_config_compare(struct drm_device *dev, bool adjust) { bool ret = true; + struct intel_crtc *crtc = to_intel_crtc(current_config->base.crtc); + struct intel_encoder *intel_encoder; + struct intel_dsi *intel_dsi = NULL; #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ do { \ @@ -12680,6 +12683,54 @@ intel_pipe_config_compare(struct drm_device *dev, ret = false; \ } +/* + * In case of BXT DSI, HW pipe_config will be retrieved from the port's timing + * configuration. This retrival includes some errors due to the DIV_ROUND_UP. + * So we are considering the max possible error at the comparison. + */ +/* + * htotal = hactive + hfp + hsync + hbp. Here last three lements might have + * the converson error, hence we consider the 3 times of error as tolerance. + */ + +#define MAX_BXT_DSI_TIMING_RETRIVAL_ERR \ + (intel_dsi == NULL ? 0 : \ + DIV_ROUND_UP((3 * 8 * intel_dsi->lane_count * 100), \ + (dsi_pixel_format_bpp(intel_dsi->pixel_format) * \ + intel_dsi->burst_mode_ratio))) + +#define BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) { \ + for_each_encoder_on_crtc(dev, &crtc->base, \ + intel_encoder) { \ + if (intel_encoder->type == INTEL_OUTPUT_DSI) { \ + intel_dsi = enc_to_intel_dsi(&intel_encoder->base); \ + } \ + } \ + if (!(current_config->name < pipe_config->name && \ + current_config->name >= (pipe_config->name - \ + MAX_BXT_DSI_TIMING_RETRIVAL_ERR))) { \ + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ + "(expected %i, found %i(Err tolerance considered))\n", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} + +#define PIPE_CONF_CHECK_I_RANGE(name) { \ + if (current_config->name != pipe_config->name) { \ + if (IS_BROXTON(dev) && crtc->config->has_dsi_encoder) { \ + BXT_DSI_PIPE_CONF_CHECK_I_RANGE(name) \ + } else { \ + INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ + "(expected %i, found %i)\n", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ + } \ +} + #define PIPE_CONF_CHECK_M_N(name) \ if (!intel_compare_link_m_n(¤t_config->name, \ &pipe_config->name,\ @@ -12784,11 +12835,11 @@ intel_pipe_config_compare(struct drm_device *dev, PIPE_CONF_CHECK_I(has_dsi_encoder); PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); - PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); + PIPE_CONF_CHECK_I_RANGE(base.adjusted_mode.crtc_htotal); + PIPE_CONF_CHECK_I_RANGE(base.adjusted_mode.crtc_hblank_start); + PIPE_CONF_CHECK_I_RANGE(base.adjusted_mode.crtc_hblank_end); + PIPE_CONF_CHECK_I_RANGE(base.adjusted_mode.crtc_hsync_start); + PIPE_CONF_CHECK_I_RANGE(base.adjusted_mode.crtc_hsync_end); PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); @@ -12866,6 +12917,7 @@ intel_pipe_config_compare(struct drm_device *dev, #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_I_RANGE #undef PIPE_CONF_CHECK_I_ALT #undef PIPE_CONF_CHECK_FLAGS #undef PIPE_CONF_CHECK_CLOCK_FUZZY