From patchwork Wed Mar 16 12:52:10 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 8599771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8425FC0553 for ; Wed, 16 Mar 2016 12:52:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8C44C20251 for ; Wed, 16 Mar 2016 12:52:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 846022021F for ; Wed, 16 Mar 2016 12:52:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDF396E2B1; Wed, 16 Mar 2016 12:52:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id A2CEA6E2B1 for ; Wed, 16 Mar 2016 12:52:50 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 16 Mar 2016 05:52:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,344,1455004800"; d="scan'208";a="670553915" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by FMSMGA003.fm.intel.com with ESMTP; 16 Mar 2016 05:52:24 -0700 Received: from mwiniars-desk1.ger.corp.intel.com (172.28.173.39) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server id 14.3.248.2; Wed, 16 Mar 2016 12:52:21 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Wed, 16 Mar 2016 13:52:10 +0100 Message-ID: <1458132730-23540-1-git-send-email-michal.winiarski@intel.com> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1458064441-22786-1-git-send-email-michal.winiarski@intel.com> References: <1458064441-22786-1-git-send-email-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.173.39] Subject: [Intel-gfx] [PATCH i-g-t v2] igt/gem_pipe_control_store_loop: Add qword write tests X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Test description suggested that all platforms were testing qword writes, while in fact only gen4-gen5 did. v2: Test dword/qword writes for all available platforms Cc: Chris Wilson Signed-off-by: Micha? Winiarski --- tests/gem_pipe_control_store_loop.c | 49 +++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c index a155ad1..cab3ed5 100644 --- a/tests/gem_pipe_control_store_loop.c +++ b/tests/gem_pipe_control_store_loop.c @@ -26,7 +26,7 @@ */ /* - * Testcase: (TLB-)Coherency of pipe_control QW writes + * Testcase: (TLB-)Coherency of pipe_control writes * * Writes a counter-value into an always newly allocated target bo (by disabling * buffer reuse). Decently trashes on tlb inconsistencies, too. @@ -43,7 +43,7 @@ #include "drm.h" #include "intel_bufmgr.h" -IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes."); +IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control writes."); static drm_intel_bufmgr *bufmgr; struct intel_batchbuffer *batch; @@ -60,13 +60,20 @@ uint32_t devid; #define PIPE_CONTROL_CS_STALL (1<<20) #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ +#define PIPE_CONTROL_STATE_BUFFER_REUSED (1 << 0) +#define PIPE_CONTROL_STATE_QWORD_WRITE (1 << 1) +#define PIPE_CONTROL_STATE_ALL_FLAGS (PIPE_CONTROL_STATE_BUFFER_REUSED | \ + PIPE_CONTROL_STATE_QWORD_WRITE) + /* Like the store dword test, but we create new command buffers each time */ static void -store_pipe_control_loop(bool preuse_buffer) +store_pipe_control_loop(uint32_t flags) { int i, val = 0; uint32_t *buf; drm_intel_bo *target_bo; + const bool preuse_buffer = flags & PIPE_CONTROL_STATE_BUFFER_REUSED; + const bool qword_write = flags & PIPE_CONTROL_STATE_QWORD_WRITE; for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) { /* we want to check tlb consistency of the pipe_control target, @@ -98,15 +105,16 @@ store_pipe_control_loop(bool preuse_buffer) * creating new batchbuffers - with buffer reuse disabled, the * support code will do that for us. */ if (batch->gen >= 8) { - BEGIN_BATCH(4, 1); - OUT_BATCH(GFX_OP_PIPE_CONTROL + 1); + BEGIN_BATCH(4 + qword_write, 1); + OUT_BATCH(GFX_OP_PIPE_CONTROL + 1 + qword_write); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC_FENCED(target_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, PIPE_CONTROL_GLOBAL_GTT); OUT_BATCH(val); /* write data */ + if (qword_write) + OUT_BATCH(~val); /* high dword */ ADVANCE_BATCH(); - } else if (batch->gen >= 6) { /* work-around hw issue, see intel_emit_post_sync_nonzero_flush * in mesa sources. */ @@ -118,24 +126,27 @@ store_pipe_control_loop(bool preuse_buffer) OUT_BATCH(0); /* write data */ ADVANCE_BATCH(); - BEGIN_BATCH(4, 1); - OUT_BATCH(GFX_OP_PIPE_CONTROL); + BEGIN_BATCH(4 + qword_write, 1); + OUT_BATCH(GFX_OP_PIPE_CONTROL + qword_write); OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE); OUT_RELOC(target_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, PIPE_CONTROL_GLOBAL_GTT); OUT_BATCH(val); /* write data */ + if (qword_write) + OUT_BATCH(~val); /* high dword */ ADVANCE_BATCH(); } else if (batch->gen >= 4) { - BEGIN_BATCH(4, 1); + BEGIN_BATCH(3 + qword_write, 1); OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | - PIPE_CONTROL_WRITE_IMMEDIATE | 2); + PIPE_CONTROL_WRITE_IMMEDIATE | (1 + qword_write)); OUT_RELOC(target_bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, PIPE_CONTROL_GLOBAL_GTT); OUT_BATCH(val); - OUT_BATCH(0xdeadbeef); + if (qword_write) + OUT_BATCH(~val); /* high dword */ ADVANCE_BATCH(); } @@ -145,6 +156,8 @@ store_pipe_control_loop(bool preuse_buffer) buf = target_bo->virtual; igt_assert(buf[0] == val); + if (qword_write) + igt_assert(buf[1] == ~val); drm_intel_bo_unmap(target_bo); /* Make doublesure that this buffer won't get reused. */ @@ -178,11 +191,15 @@ igt_main igt_assert(batch); } - igt_subtest("fresh-buffer") - store_pipe_control_loop(false); - - igt_subtest("reused-buffer") - store_pipe_control_loop(true); + for (uint32_t flags = 0; flags < PIPE_CONTROL_STATE_ALL_FLAGS + 1; flags++) { + igt_subtest_f("%sbuffer%s", + flags & PIPE_CONTROL_STATE_BUFFER_REUSED ? + "reused-" : "fresh-", + flags & PIPE_CONTROL_STATE_QWORD_WRITE ? + "-qword-write" : "") { + store_pipe_control_loop(flags); + } + } igt_fixture { intel_batchbuffer_free(batch);