From patchwork Fri Mar 18 20:07:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 8623641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4C9DAC0553 for ; Fri, 18 Mar 2016 20:08:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5515B20160 for ; Fri, 18 Mar 2016 20:08:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 6522A20218 for ; Fri, 18 Mar 2016 20:08:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D6A876E14E; Fri, 18 Mar 2016 20:08:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 714DB6E149 for ; Fri, 18 Mar 2016 20:08:06 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP; 18 Mar 2016 13:08:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,356,1455004800"; d="scan'208";a="672062466" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by FMSMGA003.fm.intel.com with ESMTP; 18 Mar 2016 13:08:05 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Fri, 18 Mar 2016 20:07:54 +0000 Message-Id: <1458331676-567-2-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458331676-567-1-git-send-email-arun.siluvery@linux.intel.com> References: <1458331676-567-1-git-send-email-arun.siluvery@linux.intel.com> Cc: Tomas Elf , Mika Kuoppala Subject: [Intel-gfx] [PATCH 1/3] drm/i915/tdr: Initialize hangcheck struct for each engine X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomas Elf Initialize hangcheck struct during driver load. Since we do the same after recovering from a reset, this is extracted into a helper function. Cc: Mika Kuoppala Signed-off-by: Tomas Elf Signed-off-by: Arun Siluvery Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_dma.c | 12 ++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 ++++++- 4 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 3f439a0..c5d1673 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -945,6 +945,16 @@ static void intel_init_dpio(struct drm_i915_private *dev_priv) } } +static void i915_hangcheck_init(struct drm_device *dev) +{ + int i; + struct intel_engine_cs *engine; + struct drm_i915_private *dev_priv = dev->dev_private; + + for_each_engine(engine, dev_priv, i) + intel_engine_init_hangcheck(engine); +} + static int i915_workqueues_init(struct drm_i915_private *dev_priv) { /* @@ -1233,6 +1243,8 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) i915_gem_load_init_fences(dev_priv); + i915_hangcheck_init(dev); + /* On the 945G/GM, the chipset reports the MSI capability on the * integrated graphics even though the support isn't actually there * according to the published specs. It doesn't appear to function diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f330a53..549a232 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2718,6 +2718,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask); extern bool intel_has_gpu_reset(struct drm_device *dev); extern int i915_reset(struct drm_device *dev); +extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3a23b95..40ef4ea 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1606,7 +1606,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) engine->next_context_status_buffer = next_context_status_buffer_hw; DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); return 0; } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index df0ef5b..ce59850 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -555,6 +555,11 @@ static bool stop_ring(struct intel_engine_cs *engine) return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; } +void intel_engine_init_hangcheck(struct intel_engine_cs *engine) +{ + memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); +} + static int init_ring_common(struct intel_engine_cs *engine) { struct drm_device *dev = engine->dev; @@ -634,7 +639,7 @@ static int init_ring_common(struct intel_engine_cs *engine) ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR; intel_ring_update_space(ringbuf); - memset(&engine->hangcheck, 0, sizeof(engine->hangcheck)); + intel_engine_init_hangcheck(engine); out: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);