From patchwork Mon Mar 21 19:26:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 8636031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B9EEC0553 for ; Mon, 21 Mar 2016 20:54:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9086620173 for ; Mon, 21 Mar 2016 20:54:56 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id A8AA42010E for ; Mon, 21 Mar 2016 20:54:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCB136E6D2; Mon, 21 Mar 2016 20:51:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id D21026E063 for ; Mon, 21 Mar 2016 19:27:08 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 21 Mar 2016 12:27:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,373,1455004800"; d="scan'208";a="673356244" Received: from smuhhunt-mobl2.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.254.185.116]) by FMSMGA003.fm.intel.com with ESMTP; 21 Mar 2016 12:27:07 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 21 Mar 2016 16:26:56 -0300 Message-Id: <1458588418-31129-4-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1458588418-31129-1-git-send-email-paulo.r.zanoni@intel.com> References: <1458588418-31129-1-git-send-email-paulo.r.zanoni@intel.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 2/4] drm/i915/fbc: sanitize i915.enable_fbc during FBC init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DDX driver changes its behavior depending on the value it reads from i915.enable_fbc, so sanitize the value in order to allow it to know what's going on. It uses this in order to choose the defaults for the TearFree option. Before this patch, it will read -1 and always assume that FBC is disabled, so it won't force TearFree. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index b8ba79c..7101880 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -823,21 +823,14 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct intel_fbc *fbc = &dev_priv->fbc; - bool enable_by_default = IS_HASWELL(dev_priv) || - IS_BROADWELL(dev_priv); if (intel_vgpu_active(dev_priv->dev)) { fbc->no_fbc_reason = "VGPU is active"; return false; } - if (i915.enable_fbc < 0 && !enable_by_default) { - fbc->no_fbc_reason = "disabled per chip default"; - return false; - } - if (!i915.enable_fbc) { - fbc->no_fbc_reason = "disabled per module param"; + fbc->no_fbc_reason = "disabled per module param or by default"; return false; } @@ -1239,6 +1232,16 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) fbc->active = false; fbc->work.scheduled = false; + /* The DDX driver changes its behavior depending on the value it reads + * from i915.enable_fbc, so sanitize the value in order to allow it to + * know what's going on. */ + if (i915.enable_fbc < 0) { + i915.enable_fbc = IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv); + DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", + i915.enable_fbc); + } + if (!HAS_FBC(dev_priv)) { fbc->no_fbc_reason = "unsupported by this chipset"; return;