From patchwork Tue Mar 22 11:48:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 8641441 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B64BAC0553 for ; Tue, 22 Mar 2016 11:48:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C4D3E202B8 for ; Tue, 22 Mar 2016 11:48:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id D090620254 for ; Tue, 22 Mar 2016 11:48:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B6B989B99; Tue, 22 Mar 2016 11:48:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 544FC6E2B7 for ; Tue, 22 Mar 2016 11:48:36 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 22 Mar 2016 04:48:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,376,1455004800"; d="scan'208";a="939089679" Received: from dsgordon-linux2.isw.intel.com ([10.102.226.88]) by orsmga002.jf.intel.com with ESMTP; 22 Mar 2016 04:48:31 -0700 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Tue, 22 Mar 2016 11:48:20 +0000 Message-Id: <1458647300-30914-2-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458647300-30914-1-git-send-email-david.s.gordon@intel.com> References: <56F0120D.201@intel.com> <1458647300-30914-1-git-send-email-david.s.gordon@intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH v3 2/2] drm/i915: tidy up a few more references to engine[] X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Now that we have a name for the previously anonymous per-engine structure embedded inside the intel_context for the benefit of execlist mode, we can optimise a few more places that access this array of structures. This may improve the compiler's ability to avoid redundant dereference and index operations. Signed-off-by: Dave Gordon --- drivers/gpu/drm/i915/i915_debugfs.c | 13 +++++-------- drivers/gpu/drm/i915/i915_guc_submission.c | 17 +++++++++-------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ccdca2c..ce3b5e9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1966,16 +1966,13 @@ static int i915_context_status(struct seq_file *m, void *unused) if (i915.enable_execlists) { seq_putc(m, '\n'); for_each_engine(engine, dev_priv, i) { - struct drm_i915_gem_object *ctx_obj = - ctx->engine[i].state; - struct intel_ringbuffer *ringbuf = - ctx->engine[i].ringbuf; + struct intel_engine_ctx *ectx = &ctx->engine[i]; seq_printf(m, "%s: ", engine->name); - if (ctx_obj) - describe_obj(m, ctx_obj); - if (ringbuf) - describe_ctx_ringbuf(m, ringbuf); + if (ectx->state) + describe_obj(m, ectx->state); + if (ectx->ringbuf) + describe_ctx_ringbuf(m, ectx->ringbuf); seq_putc(m, '\n'); } } else { diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index ae1f58d..7352023 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -392,6 +392,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc, for_each_engine(engine, dev_priv, i) { struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id]; + struct intel_engine_ctx *ectx = &ctx->engine[i]; struct drm_i915_gem_object *obj; uint64_t ctx_desc; @@ -402,7 +403,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc, * for now who owns a GuC client. But for future owner of GuC * client, need to make sure lrc is pinned prior to enter here. */ - obj = ctx->engine[i].state; + obj = ectx->state; if (!obj) break; /* XXX: continue? */ @@ -415,7 +416,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc, lrc->context_id = (client->ctx_index << GUC_ELC_CTXID_OFFSET) | (engine->guc_id << GUC_ELC_ENGINE_OFFSET); - obj = ctx->engine[i].ringbuf->obj; + obj = ectx->ringbuf->obj; lrc->ring_begin = i915_gem_obj_ggtt_offset(obj); lrc->ring_end = lrc->ring_begin + obj->base.size - 1; @@ -987,19 +988,19 @@ int intel_guc_suspend(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_guc *guc = &dev_priv->guc; - struct intel_context *ctx; + struct intel_engine_ctx *ectx; u32 data[3]; if (!i915.enable_guc_submission) return 0; - ctx = dev_priv->kernel_context; + ectx = &dev_priv->kernel_context->engine[RCS]; data[0] = HOST2GUC_ACTION_ENTER_S_STATE; /* any value greater than GUC_POWER_D0 */ data[1] = GUC_POWER_D1; /* first page is shared data with GuC */ - data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); + data[2] = i915_gem_obj_ggtt_offset(ectx->state); return host2guc_action(guc, data, ARRAY_SIZE(data)); } @@ -1013,18 +1014,18 @@ int intel_guc_resume(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_guc *guc = &dev_priv->guc; - struct intel_context *ctx; + struct intel_engine_ctx *ectx; u32 data[3]; if (!i915.enable_guc_submission) return 0; - ctx = dev_priv->kernel_context; +; ectx = &dev_priv->kernel_context->engine[RCS]; data[0] = HOST2GUC_ACTION_EXIT_S_STATE; data[1] = GUC_POWER_D0; /* first page is shared data with GuC */ - data[2] = i915_gem_obj_ggtt_offset(ctx->engine[RCS].state); + data[2] = i915_gem_obj_ggtt_offset(ectx->state); return host2guc_action(guc, data, ARRAY_SIZE(data)); }