From patchwork Mon Apr 4 21:17:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 8744451 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 582AFC0553 for ; Mon, 4 Apr 2016 21:18:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 77BFE2013D for ; Mon, 4 Apr 2016 21:18:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 855242024F for ; Mon, 4 Apr 2016 21:18:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24E356E682; Mon, 4 Apr 2016 21:18:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id CA9486E684 for ; Mon, 4 Apr 2016 21:18:05 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 04 Apr 2016 14:17:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,442,1455004800"; d="scan'208";a="777972828" Received: from pdsanabr-mobl5.amr.corp.intel.com (HELO panetone.amr.corp.intel.com) ([10.254.177.196]) by orsmga003.jf.intel.com with ESMTP; 04 Apr 2016 14:17:27 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Mon, 4 Apr 2016 18:17:16 -0300 Message-Id: <1459804638-3588-3-git-send-email-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.8.0.rc3 In-Reply-To: <1459804638-3588-1-git-send-email-paulo.r.zanoni@intel.com> References: <1459804638-3588-1-git-send-email-paulo.r.zanoni@intel.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 2/4] drm/i915/fbc: sanitize i915.enable_fbc during FBC init X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DDX driver changes its behavior depending on the value it reads from i915.enable_fbc, so sanitize the value in order to allow it to know what's going on. It uses this in order to choose the defaults for the TearFree option. Before this patch, it will read -1 and always assume that FBC is disabled, so it won't force TearFree. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_fbc.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index fc3c094..3d84ce3 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -824,21 +824,14 @@ static bool intel_fbc_can_choose(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; struct intel_fbc *fbc = &dev_priv->fbc; - bool enable_by_default = IS_HASWELL(dev_priv) || - IS_BROADWELL(dev_priv); if (intel_vgpu_active(dev_priv->dev)) { fbc->no_fbc_reason = "VGPU is active"; return false; } - if (i915.enable_fbc < 0 && !enable_by_default) { - fbc->no_fbc_reason = "disabled per chip default"; - return false; - } - if (!i915.enable_fbc) { - fbc->no_fbc_reason = "disabled per module param"; + fbc->no_fbc_reason = "disabled per module param or by default"; return false; } @@ -1240,6 +1233,16 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) fbc->active = false; fbc->work.scheduled = false; + /* The DDX driver changes its behavior depending on the value it reads + * from i915.enable_fbc, so sanitize the value in order to allow it to + * know what's going on. */ + if (i915.enable_fbc < 0) { + i915.enable_fbc = IS_HASWELL(dev_priv) || + IS_BROADWELL(dev_priv); + DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", + i915.enable_fbc); + } + if (!HAS_FBC(dev_priv)) { fbc->no_fbc_reason = "unsupported by this chipset"; return;