| Message ID | 1460051867-23254-1-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On to, 2016-04-07 at 18:57 +0100, Dave Gordon wrote: > Where we have a suitable dev_priv pointer, we can use that rather than > 'dev' for accessing INTEL_INFO(). This removes one level of memory > reference, decreasing code size a little and possibly making everything > a little faster. We could also do this for all the macros that implicitly > use INTEL_INFO e.g. IS_CHERRYVIEW(). If applied to all macros, sounds like the right thing to do. Although, I would prefer to see s/dev_priv/i915/g and then i915->info.gen, i915- >info.is_cherryview etc. rather than dozens of macros. It's going to cause a lot of rebasing, though. So depending on when we apply dev_priv -> i915, might be or might not be worth the hassle now. Regards, Joonas > > Coccinelle: > > @dev_priv_param@ > function FUNC; > idexpression struct drm_device *DEV; > identifier DEV_PRIV; > @@ > FUNC(..., struct drm_i915_private *DEV_PRIV, ...) > { > <... > INTEL_INFO > ( > - DEV > + DEV_PRIV > ) > ...> > } > > @dev_priv_local@ > idexpression struct drm_device *DEV; > identifier DEV_PRIV; > expression E; > @@ > { > ... > ( > struct drm_i915_private *DEV_PRIV; > | > struct drm_i915_private *DEV_PRIV = E; > ) > <... > INTEL_INFO > ( > - DEV > + DEV_PRIV > ) > ...> > } > > followed by manually deleting 6 now-unused "dev" locals. > > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 66 +++++++------- > drivers/gpu/drm/i915/i915_dma.c | 30 +++--- > drivers/gpu/drm/i915/i915_drv.c | 4 +- > drivers/gpu/drm/i915/i915_gem.c | 6 +- > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +- > drivers/gpu/drm/i915/i915_gem_fence.c | 8 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +-- > drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 32 +++---- > drivers/gpu/drm/i915/i915_irq.c | 36 ++++---- > drivers/gpu/drm/i915/i915_suspend.c | 20 ++-- > drivers/gpu/drm/i915/intel_color.c | 16 ++-- > drivers/gpu/drm/i915/intel_crt.c | 6 +- > drivers/gpu/drm/i915/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/intel_display.c | 141 ++++++++++++++--------------- > drivers/gpu/drm/i915/intel_dp.c | 20 ++-- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/intel_fbdev.c | 4 +- > drivers/gpu/drm/i915/intel_lrc.c | 2 +- > drivers/gpu/drm/i915/intel_lvds.c | 4 +- > drivers/gpu/drm/i915/intel_overlay.c | 4 +- > drivers/gpu/drm/i915/intel_pm.c | 50 +++++----- > drivers/gpu/drm/i915/intel_psr.c | 6 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++++---- > drivers/gpu/drm/i915/intel_sdvo.c | 8 +- > drivers/gpu/drm/i915/intel_tv.c | 2 +- > drivers/gpu/drm/i915/intel_uncore.c | 6 +- > 28 files changed, 270 insertions(+), 277 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index be4bcdc..d7f471b 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -612,7 +612,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) > seq_puts(m, "Stall check waiting for page flip ioctl, "); > seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); > else > addr = I915_READ(DSPADDR(crtc->plane)); > @@ -809,7 +809,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(GEN8_PCU_IIR)); > seq_printf(m, "PCU interrupt enable:\t%08x\n", > I915_READ(GEN8_PCU_IER)); > - } else if (INTEL_INFO(dev)->gen >= 8) { > + } else if (INTEL_INFO(dev_priv)->gen >= 8) { > seq_printf(m, "Master Interrupt Control:\t%08x\n", > I915_READ(GEN8_MASTER_IRQ)); > > @@ -935,7 +935,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(GTIMR)); > } > for_each_engine(engine, dev_priv) { > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > seq_printf(m, > "Graphics Interrupt mask (%s): %08x\n", > engine->name, I915_READ_IMR(engine)); > @@ -1172,7 +1172,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > "efficient (RPe) frequency: %d MHz\n", > intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); > mutex_unlock(&dev_priv->rps.hw_lock); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > u32 rp_state_limits; > u32 gt_perf_status; > u32 rp_state_cap; > @@ -1680,7 +1680,7 @@ static int i915_fbc_fc_get(void *data, u64 *val) > struct drm_device *dev = data; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) > + if (INTEL_INFO(dev_priv)->gen < 7 || !HAS_FBC(dev)) > return -ENODEV; > > *val = dev_priv->fbc.false_color; > @@ -1694,7 +1694,7 @@ static int i915_fbc_fc_set(void *data, u64 val) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 reg; > > - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) > + if (INTEL_INFO(dev_priv)->gen < 7 || !HAS_FBC(dev)) > return -ENODEV; > > mutex_lock(&dev_priv->fbc.lock); > @@ -1730,7 +1730,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) > seq_printf(m, "Enabled by kernel parameter: %s\n", > yesno(i915.enable_ips)); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > seq_puts(m, "Currently: unknown\n"); > } else { > if (I915_READ(IPS_CTL) & IPS_ENABLE) > @@ -2201,7 +2201,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > I915_READ16(C0DRB3)); > seq_printf(m, "C1DRB3 = 0x%04x\n", > I915_READ16(C1DRB3)); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", > I915_READ(MAD_DIMM_C0)); > seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", > @@ -2210,7 +2210,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > I915_READ(MAD_DIMM_C2)); > seq_printf(m, "TILECTL = 0x%08x\n", > I915_READ(TILECTL)); > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_INFO(dev_priv)->gen >= 8) > seq_printf(m, "GAMTARBMODE = 0x%08x\n", > I915_READ(GAMTARBMODE)); > else > @@ -2276,12 +2276,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_engine_cs *engine; > > - if (INTEL_INFO(dev)->gen == 6) > + if (INTEL_INFO(dev_priv)->gen == 6) > seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); > > for_each_engine(engine, dev_priv) { > seq_printf(m, "%s\n", engine->name); > - if (INTEL_INFO(dev)->gen == 7) > + if (INTEL_INFO(dev_priv)->gen == 7) > seq_printf(m, "GFX_MODE: 0x%08x\n", > I915_READ(RING_MODE_GEN7(engine))); > seq_printf(m, "PP_DIR_BASE: 0x%08x\n", > @@ -2315,9 +2315,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) > return ret; > intel_runtime_pm_get(dev_priv); > > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_INFO(dev_priv)->gen >= 8) > gen8_ppgtt_info(m, dev); > - else if (INTEL_INFO(dev)->gen >= 6) > + else if (INTEL_INFO(dev_priv)->gen >= 6) > gen6_ppgtt_info(m, dev); > > list_for_each_entry_reverse(file, &dev->filelist, lhead) { > @@ -2669,7 +2669,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data) > u64 power; > u32 units; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > @@ -3137,7 +3137,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused) > struct drm_device *dev = node->minor->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_engine_cs *engine; > - int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); > + int num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); > enum intel_engine_id id; > int j, ret; > > @@ -3282,7 +3282,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) > enum pipe pipe; > int plane; > > - if (INTEL_INFO(dev)->gen < 9) > + if (INTEL_INFO(dev_priv)->gen < 9) > return 0; > > drm_modeset_lock_all(dev); > @@ -4034,7 +4034,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, > > if (IS_GEN2(dev)) > ret = i8xx_pipe_crc_ctl_reg(&source, &val); > - else if (INTEL_INFO(dev)->gen < 5) > + else if (INTEL_INFO(dev_priv)->gen < 5) > ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); > else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) > ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); > @@ -4521,7 +4521,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.pri_latency; > @@ -4537,7 +4537,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.spr_latency; > @@ -4553,7 +4553,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.cur_latency; > @@ -4644,7 +4644,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.pri_latency; > @@ -4660,7 +4660,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.spr_latency; > @@ -4676,7 +4676,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.cur_latency; > @@ -4916,7 +4916,7 @@ i915_max_freq_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -4939,7 +4939,7 @@ i915_max_freq_set(void *data, u64 val) > u32 hw_max, hw_min; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -4983,7 +4983,7 @@ i915_min_freq_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -5006,7 +5006,7 @@ i915_min_freq_set(void *data, u64 val) > u32 hw_max, hw_min; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -5178,7 +5178,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, > stat->slice_total++; > > if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > - ss_cnt = INTEL_INFO(dev)->subslice_per_slice; > + ss_cnt = INTEL_INFO(dev_priv)->subslice_per_slice; > > for (ss = 0; ss < ss_max; ss++) { > unsigned int eu_cnt; > @@ -5214,15 +5214,15 @@ static void broadwell_sseu_device_status(struct drm_device *dev, > stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); > > if (stat->slice_total) { > - stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; > + stat->subslice_per_slice = INTEL_INFO(dev_priv)->subslice_per_slice; > stat->subslice_total = stat->slice_total * > stat->subslice_per_slice; > - stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; > + stat->eu_per_subslice = INTEL_INFO(dev_priv)->eu_per_subslice; > stat->eu_total = stat->eu_per_subslice * stat->subslice_total; > > /* subtract fused off EU(s) from enabled slice(s) */ > for (s = 0; s < stat->slice_total; s++) { > - u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; > + u8 subslice_7eu = INTEL_INFO(dev_priv)->subslice_7eu[s]; > > stat->eu_total -= hweight8(subslice_7eu); > } > @@ -5284,7 +5284,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) > struct drm_device *dev = inode->i_private; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return 0; > > intel_runtime_pm_get(dev_priv); > @@ -5298,7 +5298,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) > struct drm_device *dev = inode->i_private; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return 0; > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index b377753..fcdb1e0 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -165,7 +165,7 @@ static int i915_getparam(struct drm_device *dev, void *data, > value = 1; > break; > case I915_PARAM_HAS_EXEC_CONSTANTS: > - value = INTEL_INFO(dev)->gen >= 4; > + value = INTEL_INFO(dev_priv)->gen >= 4; > break; > case I915_PARAM_HAS_RELAXED_DELTA: > value = 1; > @@ -213,12 +213,12 @@ static int i915_getparam(struct drm_device *dev, void *data, > value = 1; > break; > case I915_PARAM_SUBSLICE_TOTAL: > - value = INTEL_INFO(dev)->subslice_total; > + value = INTEL_INFO(dev_priv)->subslice_total; > if (!value) > return -ENODEV; > break; > case I915_PARAM_EU_TOTAL: > - value = INTEL_INFO(dev)->eu_total; > + value = INTEL_INFO(dev_priv)->eu_total; > if (!value) > return -ENODEV; > break; > @@ -269,12 +269,12 @@ static int > intel_alloc_mchbar_resource(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp_lo, temp_hi = 0; > u64 mchbar_addr; > int ret; > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); > pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); > mchbar_addr = ((u64)temp_hi << 32) | temp_lo; > @@ -301,7 +301,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) > return ret; > } > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > pci_write_config_dword(dev_priv->bridge_dev, reg + 4, > upper_32_bits(dev_priv->mch_res.start)); > > @@ -315,7 +315,7 @@ static void > intel_setup_mchbar(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int mchbar_reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp; > bool enabled; > > @@ -355,7 +355,7 @@ static void > intel_teardown_mchbar(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int mchbar_reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp; > > if (dev_priv->mchbar_need_disable) { > @@ -479,7 +479,7 @@ static int i915_load_modeset_init(struct drm_device *dev) > /* Always safe in the mode setting case. */ > /* FIXME: do pre/post-mode set stuff in core KMS code */ > dev->vblank_disable_allowed = true; > - if (INTEL_INFO(dev)->num_pipes == 0) > + if (INTEL_INFO(dev_priv)->num_pipes == 0) > return 0; > > ret = intel_fbdev_init(dev); > @@ -853,7 +853,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > DRM_INFO("Display disabled (module parameter)\n"); > info->num_pipes = 0; > } else if (info->num_pipes > 0 && > - (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && > + (INTEL_INFO(dev_priv)->gen == 7 || INTEL_INFO(dev_priv)->gen == 8) && > HAS_PCH_SPLIT(dev)) { > u32 fuse_strap = I915_READ(FUSE_STRAP); > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > @@ -877,7 +877,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > DRM_INFO("PipeC fused off\n"); > info->num_pipes -= 1; > } > - } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { > + } else if (info->num_pipes > 0 && INTEL_INFO(dev_priv)->gen == 9) { > u32 dfsm = I915_READ(SKL_DFSM); > u8 disabled_mask = 0; > bool invalid; > @@ -915,7 +915,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > cherryview_sseu_info_init(dev); > else if (IS_BROADWELL(dev)) > broadwell_sseu_info_init(dev); > - else if (INTEL_INFO(dev)->gen >= 9) > + else if (INTEL_INFO(dev_priv)->gen >= 9) > gen9_sseu_info_init(dev); > > /* Snooping is broken on BXT A stepping. */ > @@ -1091,7 +1091,7 @@ static int i915_mmio_setup(struct drm_device *dev) > * the register BAR remains the same size for all the earlier > * generations up to Ironlake. > */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_INFO(dev_priv)->gen < 5) > mmio_size = 512 * 1024; > else > mmio_size = 2 * 1024 * 1024; > @@ -1373,8 +1373,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) > * of the i915_driver_init_/i915_driver_register functions according > * to the role/effect of the given init step. > */ > - if (INTEL_INFO(dev)->num_pipes) { > - ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); > + if (INTEL_INFO(dev_priv)->num_pipes) { > + ret = drm_vblank_init(dev, INTEL_INFO(dev_priv)->num_pipes); > if (ret) > goto out_cleanup_hw; > } > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 29b4e79..d50de67 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -458,7 +458,7 @@ void intel_detect_pch(struct drm_device *dev) > /* In all current cases, num_pipes is equivalent to the PCH_NOP setting > * (which really amounts to a PCH but no South Display). > */ > - if (INTEL_INFO(dev)->num_pipes == 0) { > + if (INTEL_INFO(dev_priv)->num_pipes == 0) { > dev_priv->pch_type = PCH_NOP; > return; > } > @@ -949,7 +949,7 @@ int i915_reset(struct drm_device *dev) > * previous concerns that it doesn't respond well to some forms > * of re-init after reset. > */ > - if (INTEL_INFO(dev)->gen > 5) > + if (INTEL_INFO(dev_priv)->gen > 5) > intel_enable_gt_powersave(dev); > > return 0; > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index b342f67..9d13a70 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4730,7 +4730,7 @@ void i915_gem_init_swizzling(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 5 || > + if (INTEL_INFO(dev_priv)->gen < 5 || > dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) > return; > > @@ -4832,7 +4832,7 @@ i915_gem_init_hw(struct drm_device *dev) > struct intel_engine_cs *engine; > int ret, j; > > - if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) > + if (INTEL_INFO(dev_priv)->gen < 6 && !intel_enable_gtt()) > return -EIO; > > /* Double layer security blanket, see i915_gem_init() */ > @@ -4850,7 +4850,7 @@ i915_gem_init_hw(struct drm_device *dev) > u32 temp = I915_READ(GEN7_MSG_CTL); > temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); > I915_WRITE(GEN7_MSG_CTL, temp); > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_INFO(dev_priv)->gen >= 7) { > u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); > temp &= ~RESET_PCH_HANDSHAKE_ENABLE; > I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index fe580cb..92ae104 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -111,7 +111,7 @@ static int get_context_size(struct drm_device *dev) > int ret; > u32 reg; > > - switch (INTEL_INFO(dev)->gen) { > + switch (INTEL_INFO(dev_priv)->gen) { > case 6: > reg = I915_READ(CXT_SIZE); > ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 0ee61fd..cd6a25c 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -335,7 +335,7 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj, > offset & PAGE_MASK); > iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > offset += sizeof(uint32_t); > > if (offset_in_page(offset) == 0) { > @@ -1264,19 +1264,19 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, > } > > if (instp_mode != dev_priv->relative_constants_mode) { > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > DRM_DEBUG("no rel constants on pre-gen4\n"); > return -EINVAL; > } > > - if (INTEL_INFO(dev)->gen > 5 && > + if (INTEL_INFO(dev_priv)->gen > 5 && > instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { > DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); > return -EINVAL; > } > > /* The HW changed the meaning on this bit on gen6 */ > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_INFO(dev_priv)->gen >= 6) > instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; > } > break; > diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c > index a2b938e..b8c810f 100644 > --- a/drivers/gpu/drm/i915/i915_gem_fence.c > +++ b/drivers/gpu/drm/i915/i915_gem_fence.c > @@ -62,7 +62,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg, > i915_reg_t fence_reg_lo, fence_reg_hi; > int fence_pitch_shift; > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > fence_reg_lo = FENCE_REG_GEN6_LO(reg); > fence_reg_hi = FENCE_REG_GEN6_HI(reg); > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; > @@ -209,7 +209,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, > i830_write_fence_reg(dev, reg, obj); > else if (IS_GEN3(dev)) > i915_write_fence_reg(dev, reg, obj); > - else if (INTEL_INFO(dev)->gen >= 4) > + else if (INTEL_INFO(dev_priv)->gen >= 4) > i965_write_fence_reg(dev, reg, obj); > > /* And similarly be paranoid that no direct access to this region > @@ -553,7 +553,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) > uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; > uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; > > - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { > + if (INTEL_INFO(dev_priv)->gen >= 8 || IS_VALLEYVIEW(dev)) { > /* > * On BDW+, swizzling is not used. We leave the CPU memory > * controller in charge of optimizing memory accesses without > @@ -563,7 +563,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) > */ > swizzle_x = I915_BIT_6_SWIZZLE_NONE; > swizzle_y = I915_BIT_6_SWIZZLE_NONE; > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > if (dev_priv->preserve_bios_swizzle) { > if (I915_READ(DISP_ARB_CTL) & > DISP_TILE_SURFACE_SWIZZLING) { > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index da6e3a5..59aefbd 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2281,7 +2281,7 @@ void i915_check_and_clear_faults(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_engine_cs *engine; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return; > > for_each_engine(engine, dev_priv) { > @@ -2322,7 +2322,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) > /* Don't bother messing with faults pre GEN6 as we have little > * documentation supporting that it's a good idea. > */ > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return; > > i915_check_and_clear_faults(dev); > @@ -3050,7 +3050,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > > pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); > ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); > } else if (IS_CHERRYVIEW(dev)) { > @@ -3166,10 +3166,10 @@ int i915_ggtt_init_hw(struct drm_device *dev) > struct i915_ggtt *ggtt = &dev_priv->ggtt; > int ret; > > - if (INTEL_INFO(dev)->gen <= 5) { > + if (INTEL_INFO(dev_priv)->gen <= 5) { > ggtt->probe = i915_gmch_probe; > ggtt->base.cleanup = i915_gmch_remove; > - } else if (INTEL_INFO(dev)->gen < 8) { > + } else if (INTEL_INFO(dev_priv)->gen < 8) { > ggtt->probe = gen6_gmch_probe; > ggtt->base.cleanup = gen6_gmch_remove; > if (IS_HASWELL(dev) && dev_priv->ellc_size) > @@ -3178,7 +3178,7 @@ int i915_ggtt_init_hw(struct drm_device *dev) > ggtt->base.pte_encode = hsw_pte_encode; > else if (IS_VALLEYVIEW(dev)) > ggtt->base.pte_encode = byt_pte_encode; > - else if (INTEL_INFO(dev)->gen >= 7) > + else if (INTEL_INFO(dev_priv)->gen >= 7) > ggtt->base.pte_encode = ivb_pte_encode; > else > ggtt->base.pte_encode = snb_pte_encode; > @@ -3267,7 +3267,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) > i915_gem_clflush_object(obj, obj->pin_display); > } > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) > chv_setup_private_ppat(dev_priv); > else > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index ea06da0..fe1e5f4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -106,7 +106,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > * > */ > base = 0; > - if (INTEL_INFO(dev)->gen >= 3) { > + if (INTEL_INFO(dev_priv)->gen >= 3) { > /* Read Graphics Base of Stolen Memory directly */ > pci_read_config_dword(dev->pdev, 0x5c, &base); > base &= ~((1<<20) - 1); > @@ -188,7 +188,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > return 0; > > /* make sure we don't clobber the GTT if it's within stolen memory */ > - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { > + if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { > struct { > u32 start, end; > } stolen[2] = { > @@ -401,7 +401,7 @@ int i915_gem_init_stolen(struct drm_device *dev) > mutex_init(&dev_priv->mm.stolen_lock); > > #ifdef CONFIG_INTEL_IOMMU > - if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { > + if (intel_iommu_gfx_mapped && INTEL_INFO(dev_priv)->gen < 8) { > DRM_INFO("DMAR active, disabling use of stolen memory\n"); > return 0; > } > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 6d63a2f..fa7aaf7 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -381,7 +381,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > > err_printf(m, "EIR: 0x%08x\n", error->eir); > err_printf(m, "IER: 0x%08x\n", error->ier); > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > for (i = 0; i < 4; i++) > err_printf(m, "GTIER gt %d: 0x%08x\n", i, > error->gtier[i]); > @@ -400,17 +400,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > err_printf(m, " INSTDONE_%d: 0x%08x\n", i, > error->extra_instdone[i]); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > err_printf(m, "ERROR: 0x%08x\n", error->error); > > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_INFO(dev_priv)->gen >= 8) > err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", > error->fault_data1, error->fault_data0); > > err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); > } > > - if (INTEL_INFO(dev)->gen == 7) > + if (INTEL_INFO(dev_priv)->gen == 7) > err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); > > for (i = 0; i < ARRAY_SIZE(error->ring); i++) > @@ -835,7 +835,7 @@ static void i915_gem_record_fences(struct drm_device *dev, > } else if (IS_GEN5(dev) || IS_GEN4(dev)) { > for (i = 0; i < dev_priv->num_fence_regs; i++) > error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > for (i = 0; i < dev_priv->num_fence_regs; i++) > error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); > } > @@ -899,24 +899,24 @@ static void i915_record_ring_state(struct drm_device *dev, > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); > ering->fault_reg = I915_READ(RING_FAULT_REG(engine)); > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_INFO(dev_priv)->gen >= 8) > gen8_record_semaphore_state(dev_priv, error, engine, > ering); > else > gen6_record_semaphore_state(dev_priv, engine, ering); > } > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); > ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); > ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); > ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base)); > ering->instps = I915_READ(RING_INSTPS(engine->mmio_base)); > ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; > ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; > } > @@ -980,7 +980,7 @@ static void i915_record_ring_state(struct drm_device *dev, > else if (IS_GEN7(dev)) > ering->vm_info.pp_dir_base = > I915_READ(RING_PP_DIR_BASE(engine)); > - else if (INTEL_INFO(dev)->gen >= 8) > + else if (INTEL_INFO(dev_priv)->gen >= 8) > for (i = 0; i < 4; i++) { > ering->vm_info.pdp[i] = > I915_READ(GEN8_RING_PDP_UDW(engine, i)); > @@ -1253,7 +1253,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > if (IS_GEN7(dev)) > error->err_int = I915_READ(GEN7_ERR_INT); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); > error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); > } > @@ -1265,10 +1265,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > } > > /* 2: Registers which belong to multiple generations */ > - if (INTEL_INFO(dev)->gen >= 7) > + if (INTEL_INFO(dev_priv)->gen >= 7) > error->forcewake = I915_READ_FW(FORCEWAKE_MT); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > error->derrmr = I915_READ(DERRMR); > error->error = I915_READ(ERROR_GEN6); > error->done_reg = I915_READ(DONE_REG); > @@ -1284,7 +1284,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > if (HAS_HW_CONTEXTS(dev)) > error->ccid = I915_READ(CCID); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > error->ier = I915_READ(GEN8_DE_MISC_IER); > for (i = 0; i < 4; i++) > error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > @@ -1315,7 +1315,7 @@ static void i915_error_capture_msg(struct drm_device *dev, > > len = scnprintf(error->error_msg, sizeof(error->error_msg), > "GPU HANG: ecode %d:%d:0x%08x", > - INTEL_INFO(dev)->gen, ring_id, ecode); > + INTEL_INFO(dev_priv)->gen, ring_id, ecode); > > if (ring_id != -1 && error->ring[ring_id].pid != -1) > len += scnprintf(error->error_msg + len, > @@ -1458,7 +1458,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) > else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { > instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); > instdone[1] = I915_READ(GEN4_INSTDONE1); > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_INFO(dev_priv)->gen >= 7) { > instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); > instdone[1] = I915_READ(GEN7_SC_INSTDONE); > instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index c36aa64..3994c89a 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -617,7 +617,7 @@ static void i915_enable_asle_pipestat(struct drm_device *dev) > spin_lock_irq(&dev_priv->irq_lock); > > i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > i915_enable_pipestat(dev_priv, PIPE_A, > PIPE_LEGACY_BLC_EVENT_STATUS); > > @@ -835,7 +835,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, > if (stime) > *stime = ktime_get(); > > - if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { > + if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev_priv)->gen >= 5) { > /* No obvious pixelcount register. Only query vertical > * scanout position from Display scan line register. > */ > @@ -897,7 +897,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, > else > position += vtotal - vbl_end; > > - if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { > + if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev_priv)->gen >= 5) { > *vpos = position; > *hpos = 0; > } else { > @@ -1591,12 +1591,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t res1, res2; > > - if (INTEL_INFO(dev)->gen >= 3) > + if (INTEL_INFO(dev_priv)->gen >= 3) > res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); > else > res1 = 0; > > - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) > + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) > res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); > else > res2 = 0; > @@ -2215,7 +2215,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) > if (gt_iir) { > I915_WRITE(GTIIR, gt_iir); > ret = IRQ_HANDLED; > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_INFO(dev_priv)->gen >= 6) > snb_gt_irq_handler(dev, dev_priv, gt_iir); > else > ilk_gt_irq_handler(dev, dev_priv, gt_iir); > @@ -2225,13 +2225,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) > if (de_iir) { > I915_WRITE(DEIIR, de_iir); > ret = IRQ_HANDLED; > - if (INTEL_INFO(dev)->gen >= 7) > + if (INTEL_INFO(dev_priv)->gen >= 7) > ivb_display_irq_handler(dev, de_iir); > else > ilk_display_irq_handler(dev, de_iir); > } > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > u32 pm_iir = I915_READ(GEN6_PMIIR); > if (pm_iir) { > I915_WRITE(GEN6_PMIIR, pm_iir); > @@ -2614,7 +2614,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev) > pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); > for (i = 0; i < ARRAY_SIZE(instdone); i++) > pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > u32 ipeir = I915_READ(IPEIR); > > pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); > @@ -2704,7 +2704,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) > unsigned long irqflags; > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > i915_enable_pipestat(dev_priv, pipe, > PIPE_START_VBLANK_INTERRUPT_STATUS); > else > @@ -2719,7 +2719,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > unsigned long irqflags; > - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > + uint32_t bit = (INTEL_INFO(dev_priv)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > DE_PIPE_VBLANK(pipe); > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > @@ -2773,7 +2773,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > unsigned long irqflags; > - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > + uint32_t bit = (INTEL_INFO(dev_priv)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > DE_PIPE_VBLANK(pipe); > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > @@ -3036,7 +3036,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) > return HANGCHECK_KICK; > } > > - if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { > + if (INTEL_INFO(dev_priv)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { > switch (semaphore_passed(engine)) { > default: > return HANGCHECK_HUNG; > @@ -3257,7 +3257,7 @@ static void gen5_gt_irq_reset(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > GEN5_IRQ_RESET(GT); > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_INFO(dev_priv)->gen >= 6) > GEN5_IRQ_RESET(GEN6_PM); > } > > @@ -3457,12 +3457,12 @@ static void ilk_hpd_irq_setup(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 hotplug_irqs, hotplug, enabled_irqs; > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; > enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); > > bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_INFO(dev_priv)->gen >= 7) { > hotplug_irqs = DE_DP_A_HOTPLUG_IVB; > enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); > > @@ -3564,7 +3564,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > > GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > /* > * RPS interrupts will get enabled/disabled on demand when RPS > * itself is enabled/disabled. > @@ -3582,7 +3582,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 display_mask, extra_mask; > > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_INFO(dev_priv)->gen >= 7) { > display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | > DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | > DE_PLANEB_FLIP_DONE_IVB | > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index 34e061a..34c9ed4 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -34,13 +34,13 @@ static void i915_save_display(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > /* Display arbitration control */ > - if (INTEL_INFO(dev)->gen <= 4) > + if (INTEL_INFO(dev_priv)->gen <= 4) > dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); > > /* LVDS state */ > if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) > dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); > - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > + else if (INTEL_INFO(dev_priv)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > dev_priv->regfile.saveLVDS = I915_READ(LVDS); > > /* Panel power sequencer */ > @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev) > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); > dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); > - } else if (INTEL_INFO(dev)->gen <= 4) { > + } else if (INTEL_INFO(dev_priv)->gen <= 4) { > dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); > @@ -57,7 +57,7 @@ static void i915_save_display(struct drm_device *dev) > } > > /* save FBC interval */ > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) > + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev)) > dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); > } > > @@ -67,7 +67,7 @@ static void i915_restore_display(struct drm_device *dev) > u32 mask = 0xffffffff; > > /* Display arbitration */ > - if (INTEL_INFO(dev)->gen <= 4) > + if (INTEL_INFO(dev_priv)->gen <= 4) > I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); > > mask = ~LVDS_PORT_EN; > @@ -75,7 +75,7 @@ static void i915_restore_display(struct drm_device *dev) > /* LVDS state */ > if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) > I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); > - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > + else if (INTEL_INFO(dev_priv)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); > > /* Panel power sequencer */ > @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev) > I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); > I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); > I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); > - } else if (INTEL_INFO(dev)->gen <= 4) { > + } else if (INTEL_INFO(dev_priv)->gen <= 4) { > I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); > I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); > I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); > @@ -95,7 +95,7 @@ static void i915_restore_display(struct drm_device *dev) > intel_fbc_global_disable(dev_priv); > > /* restore FBC interval */ > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) > + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev)) > I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); > > i915_redisable_vga(dev); > @@ -115,7 +115,7 @@ int i915_save_state(struct drm_device *dev) > &dev_priv->regfile.saveGCDGMBUS); > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_INFO(dev_priv)->gen < 7) > dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > /* Memory Arbitration state */ > @@ -161,7 +161,7 @@ int i915_restore_state(struct drm_device *dev) > i915_restore_display(dev); > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_INFO(dev_priv)->gen < 7) > I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | > 0xffff0000); > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 1b3f974..8e34020 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -179,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) > I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); > I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); > > - if (INTEL_INFO(dev)->gen > 6) { > + if (INTEL_INFO(dev_priv)->gen > 6) { > uint16_t postoff = 0; > > if (intel_crtc->config->limited_color_range) > @@ -346,7 +346,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc_state *intel_state = to_intel_crtc_state(state); > enum pipe pipe = to_intel_crtc(crtc)->pipe; > - uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size; > + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; > > if (crtc_state_is_legacy(state)) { > haswell_load_luts(state); > @@ -442,7 +442,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) > > if (state->degamma_lut) { > lut = (struct drm_color_lut *) state->degamma_lut->data; > - lut_size = INTEL_INFO(dev)->color.degamma_lut_size; > + lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; > for (i = 0; i < lut_size; i++) { > /* Write LUT in U0.14 format. */ > word0 = > @@ -457,7 +457,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) > > if (state->gamma_lut) { > lut = (struct drm_color_lut *) state->gamma_lut->data; > - lut_size = INTEL_INFO(dev)->color.gamma_lut_size; > + lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; > for (i = 0; i < lut_size; i++) { > /* Write LUT in U0.10 format. */ > word0 = > @@ -545,9 +545,9 @@ void intel_color_init(struct drm_crtc *crtc) > } > > /* Enable color management support when we have degamma & gamma LUTs. */ > - if (INTEL_INFO(dev)->color.degamma_lut_size != 0 && > - INTEL_INFO(dev)->color.gamma_lut_size != 0) > + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && > + INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) > drm_helper_crtc_enable_color_mgmt(crtc, > - INTEL_INFO(dev)->color.degamma_lut_size, > - INTEL_INFO(dev)->color.gamma_lut_size); > + INTEL_INFO(dev_priv)->color.degamma_lut_size, > + INTEL_INFO(dev_priv)->color.gamma_lut_size); > } > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index a2a31fd..bdc15a9 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -152,7 +152,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) > const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > u32 adpa; > > - if (INTEL_INFO(dev)->gen >= 5) > + if (INTEL_INFO(dev_priv)->gen >= 5) > adpa = ADPA_HOTPLUG_BITS; > else > adpa = 0; > @@ -647,7 +647,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) > if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { > if (intel_crt_detect_ddc(connector)) > status = connector_status_connected; > - else if (INTEL_INFO(dev)->gen < 4) > + else if (INTEL_INFO(dev_priv)->gen < 4) > status = intel_crt_load_detect(crt, > to_intel_crtc(connector->state->crtc)->pipe); > else if (i915.load_detect_test) > @@ -713,7 +713,7 @@ static void intel_crt_reset(struct drm_connector *connector) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crt *crt = intel_attached_crt(connector); > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_INFO(dev_priv)->gen >= 5) { > u32 adpa; > > adpa = I915_READ(crt->adpa_reg); > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 921edf1..a633155 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1657,7 +1657,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) > if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | > DPLL_CTRL2_DDI_CLK_OFF(port))); > - else if (INTEL_INFO(dev)->gen < 9) > + else if (INTEL_INFO(dev_priv)->gen < 9) > I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); > } > > @@ -1685,7 +1685,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) > } else if (type == INTEL_OUTPUT_EDP) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > - if (port == PORT_A && INTEL_INFO(dev)->gen < 9) > + if (port == PORT_A && INTEL_INFO(dev_priv)->gen < 9) > intel_dp_stop_link_train(intel_dp); > > intel_edp_backlight_on(intel_dp); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index feb7028..9420637 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1116,7 +1116,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) > enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > enum pipe pipe = crtc->pipe; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > i915_reg_t reg = PIPECONF(cpu_transcoder); > > /* Wait for the Pipe State to go off */ > @@ -1334,11 +1334,10 @@ static void assert_plane(struct drm_i915_private *dev_priv, > static void assert_planes_disabled(struct drm_i915_private *dev_priv, > enum pipe pipe) > { > - struct drm_device *dev = dev_priv->dev; > int i; > > /* Primary planes are fixed to pipes on gen4+ */ > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > u32 val = I915_READ(DSPCNTR(pipe)); > I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, > "plane %c assertion failure, should be disabled but not\n", > @@ -1363,7 +1362,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, > struct drm_device *dev = dev_priv->dev; > int sprite; > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > for_each_sprite(dev_priv, pipe, sprite) { > u32 val = I915_READ(PLANE_CTL(pipe, sprite)); > I915_STATE_WARN(val & PLANE_CTL_ENABLE, > @@ -1377,12 +1376,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > sprite_name(pipe, sprite), pipe_name(pipe)); > } > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_INFO(dev_priv)->gen >= 7) { > u32 val = I915_READ(SPRCTL(pipe)); > I915_STATE_WARN(val & SPRITE_ENABLE, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > plane_name(pipe), pipe_name(pipe)); > - } else if (INTEL_INFO(dev)->gen >= 5) { > + } else if (INTEL_INFO(dev_priv)->gen >= 5) { > u32 val = I915_READ(DVSCNTR(pipe)); > I915_STATE_WARN(val & DVS_ENABLE, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > @@ -1664,7 +1663,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > POSTING_READ(reg); > udelay(150); > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > I915_WRITE(DPLL_MD(crtc->pipe), > crtc->config->dpll_hw_state.dpll_md); > } else { > @@ -2639,7 +2638,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > > dspcntr |= DISPLAY_PLANE_ENABLE; > > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > if (intel_crtc->pipe == PIPE_B) > dspcntr |= DISPPLANE_SEL_PIPE_B; > > @@ -2684,7 +2683,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > BUG(); > } > > - if (INTEL_INFO(dev)->gen >= 4 && > + if (INTEL_INFO(dev_priv)->gen >= 4 && > obj->tiling_mode != I915_TILING_NONE) > dspcntr |= DISPPLANE_TILED; > > @@ -2693,7 +2692,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > > linear_offset = y * fb->pitches[0] + x * cpp; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > intel_crtc->dspaddr_offset = > intel_compute_tile_offset(&x, &y, fb, 0, > fb->pitches[0], rotation); > @@ -2721,7 +2720,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > I915_WRITE(reg, dspcntr); > > I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > I915_WRITE(DSPSURF(plane), > i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); > I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > @@ -3160,7 +3159,7 @@ void intel_finish_reset(struct drm_device *dev) > return; > > /* reset doesn't touch the display */ > - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { > + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) { > /* > * Flips in the rings have been nuked by the reset, > * so update the base address of all primary > @@ -3242,7 +3241,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, > (pipe_config->pipe_src_h - 1)); > > /* on skylake this is done by detaching scalers */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > skl_detach_scalers(crtc); > > if (pipe_config->pch_pfit.enabled) > @@ -4870,7 +4869,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > if (!intel_crtc->config->has_dsi_encoder) > intel_ddi_enable_pipe_clock(intel_crtc); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > skylake_pfit_enable(intel_crtc); > else > ironlake_pfit_enable(intel_crtc); > @@ -5035,7 +5034,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > if (!intel_crtc->config->has_dsi_encoder) > intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > skylake_scaler_disable(intel_crtc); > else > ironlake_pfit_disable(intel_crtc, false); > @@ -6543,7 +6542,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; > > /* FIXME should check pixel clock limits on all platforms */ > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; > > /* > @@ -6577,7 +6576,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > /* Cantiga+ cannot handle modes with a hsync front porch of 0. > * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. > */ > - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && > + if ((INTEL_INFO(dev_priv)->gen > 4 || IS_G4X(dev)) && > adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) > return -EINVAL; > > @@ -7119,7 +7118,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > int pipe = crtc->pipe; > enum transcoder transcoder = crtc->config->cpu_transcoder; > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_INFO(dev_priv)->gen >= 5) { > I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); > I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); > I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); > @@ -7128,7 +7127,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > * for gen < 8) and if DRRS is supported (to make sure the > * registers are not unnecessarily accessed). > */ > - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && > + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev_priv)->gen < 8) && > crtc->config->has_drrs) { > I915_WRITE(PIPE_DATA_M2(transcoder), > TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); > @@ -7501,7 +7500,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, > dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; > break; > } > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); > > if (crtc_state->sdvo_tv_clock) > @@ -7515,7 +7514,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, > dpll |= DPLL_VCO_ENABLE; > crtc_state->dpll_hw_state.dpll = dpll; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > u32 dpll_md = (crtc_state->pixel_multiplier - 1) > << DPLL_MD_UDI_MULTIPLIER_SHIFT; > crtc_state->dpll_hw_state.dpll_md = dpll_md; > @@ -7588,7 +7587,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) > vsyncshift += adjusted_mode->crtc_htotal; > } > > - if (INTEL_INFO(dev)->gen > 3) > + if (INTEL_INFO(dev_priv)->gen > 3) > I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); > > I915_WRITE(HTOTAL(cpu_transcoder), > @@ -7757,7 +7756,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) > } > > if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > - if (INTEL_INFO(dev)->gen < 4 || > + if (INTEL_INFO(dev_priv)->gen < 4 || > intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) > pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; > else > @@ -7975,7 +7974,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t tmp; > > - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > + if (INTEL_INFO(dev_priv)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > return; > > tmp = I915_READ(PFIT_CONTROL); > @@ -7983,7 +7982,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > return; > > /* Check whether the pfit is attached to our pipe. */ > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > if (crtc->pipe != PIPE_B) > return; > } else { > @@ -7993,7 +7992,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > > pipe_config->gmch_pfit.control = tmp; > pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_INFO(dev_priv)->gen < 5) > pipe_config->gmch_pfit.lvds_border_bits = > I915_READ(LVDS) & LVDS_BORDER_ENABLE; > } > @@ -8050,7 +8049,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, > > fb = &intel_fb->base; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > if (val & DISPPLANE_TILED) { > plane_config->tiling = I915_TILING_X; > fb->modifier[0] = I915_FORMAT_MOD_X_TILED; > @@ -8062,7 +8061,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, > fb->pixel_format = fourcc; > fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > if (plane_config->tiling) > offset = I915_READ(DSPTILEOFF(plane)); > else > @@ -8166,7 +8165,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > (tmp & PIPECONF_COLOR_RANGE_SELECT)) > pipe_config->limited_color_range = true; > > - if (INTEL_INFO(dev)->gen < 4) > + if (INTEL_INFO(dev_priv)->gen < 4) > pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; > > intel_get_pipe_timings(crtc, pipe_config); > @@ -8174,7 +8173,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > > i9xx_get_pfit_config(crtc, pipe_config); > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > /* No way to read it out on pipes B and C */ > if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) > tmp = dev_priv->chv_dpll_md[crtc->pipe]; > @@ -8954,7 +8953,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = dev->dev_private; > enum pipe pipe = crtc->pipe; > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_INFO(dev_priv)->gen >= 5) { > m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); > m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); > m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) > @@ -8966,7 +8965,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, > * gen < 8) and if DRRS is supported (to make sure the > * registers are not unnecessarily read). > */ > - if (m2_n2 && INTEL_INFO(dev)->gen < 8 && > + if (m2_n2 && INTEL_INFO(dev_priv)->gen < 8 && > crtc->config->has_drrs) { > m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); > m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); > @@ -9168,7 +9167,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, > > fb = &intel_fb->base; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > if (val & DISPPLANE_TILED) { > plane_config->tiling = I915_TILING_X; > fb->modifier[0] = I915_FORMAT_MOD_X_TILED; > @@ -9934,7 +9933,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > * DDI E. So just check whether this pipe is wired to DDI E and whether > * the PCH transcoder is on. > */ > - if (INTEL_INFO(dev)->gen < 9 && > + if (INTEL_INFO(dev_priv)->gen < 9 && > (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { > pipe_config->has_pch_encoder = true; > > @@ -9985,11 +9984,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > pipe_config->gamma_mode = > I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > skl_init_scalers(dev, crtc, pipe_config); > } > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > pipe_config->scaler_state.scaler_id = -1; > pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); > } > @@ -9997,7 +9996,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); > if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { > power_domain_mask |= BIT(power_domain); > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > skylake_get_pfit_config(crtc, pipe_config); > else > ironlake_get_pfit_config(crtc, pipe_config); > @@ -10779,7 +10778,7 @@ void intel_mark_busy(struct drm_device *dev) > > intel_runtime_pm_get(dev_priv); > i915_update_gfx_val(dev_priv); > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_INFO(dev_priv)->gen >= 6) > gen6_rps_busy(dev_priv); > dev_priv->mm.busy = true; > } > @@ -10793,7 +10792,7 @@ void intel_mark_idle(struct drm_device *dev) > > dev_priv->mm.busy = false; > > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_INFO(dev_priv)->gen >= 6) > gen6_rps_idle(dev->dev_private); > > intel_runtime_pm_put(dev_priv); > @@ -10915,7 +10914,7 @@ static bool page_flip_finished(struct intel_crtc *crtc) > * really needed there. But since ctg has the registers, > * include it in the check anyway. > */ > - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) > + if (INTEL_INFO(dev_priv)->gen < 5 && !IS_G4X(dev)) > return true; > > /* > @@ -11436,7 +11435,7 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, > > /* Potential stall - if we see that the flip has happened, > * assume a missed interrupt. */ > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); > else > addr = I915_READ(DSPADDR(intel_crtc->plane)); > @@ -11508,7 +11507,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > * TILEOFF/LINOFF registers can't be changed via MI display flips. > * Note that pitch changes could also affect these register. > */ > - if (INTEL_INFO(dev)->gen > 3 && > + if (INTEL_INFO(dev_priv)->gen > 3 && > (fb->offsets[0] != crtc->primary->fb->offsets[0] || > fb->pitches[0] != crtc->primary->fb->pitches[0])) > return -EINVAL; > @@ -11570,7 +11569,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > atomic_inc(&intel_crtc->unpin_work_count); > intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); > > - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) > + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) > work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; > > if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { > @@ -11580,7 +11579,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > engine = NULL; > } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { > engine = &dev_priv->engine[BCS]; > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_INFO(dev_priv)->gen >= 7) { > engine = i915_gem_request_get_engine(obj->last_write_req); > if (engine == NULL || engine->id != RCS) > engine = &dev_priv->engine[BCS]; > @@ -11774,7 +11773,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, > bool turn_off, turn_on, visible, was_visible; > struct drm_framebuffer *fb = plane_state->fb; > > - if (crtc_state && INTEL_INFO(dev)->gen >= 9 && > + if (crtc_state && INTEL_INFO(dev_priv)->gen >= 9 && > plane->type != DRM_PLANE_TYPE_CURSOR) { > ret = skl_update_scaler_plane( > to_intel_crtc_state(crtc_state), > @@ -11833,7 +11832,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, > > /* Pre-gen9 platforms need two-step watermark updates */ > if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && > - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) > + INTEL_INFO(dev_priv)->gen < 9 && dev_priv->display.optimize_watermarks) > to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; > > if (visible || was_visible) > @@ -11966,7 +11965,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, > } > } > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > if (mode_changed) > ret = skl_update_scaler_crtc(pipe_config); > > @@ -12763,7 +12762,7 @@ static void check_wm_state(struct drm_device *dev) > struct intel_crtc *intel_crtc; > int plane; > > - if (INTEL_INFO(dev)->gen < 9) > + if (INTEL_INFO(dev_priv)->gen < 9) > return; > > skl_ddb_get_hw_state(dev_priv, &hw_ddb); > @@ -14238,7 +14237,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > crtc_state->base.crtc = &intel_crtc->base; > > /* initialize shared scalers */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > if (pipe == PIPE_C) > intel_crtc->num_scalers = 1; > else > @@ -14266,7 +14265,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > */ > intel_crtc->pipe = pipe; > intel_crtc->plane = pipe; > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { > + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen < 4) { > DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); > intel_crtc->plane = !pipe; > } > @@ -14368,7 +14367,7 @@ static bool intel_crt_present(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > return false; > > if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) > @@ -14673,7 +14672,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > switch (mode_cmd->modifier[0]) { > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Yf_TILED: > - if (INTEL_INFO(dev)->gen < 9) { > + if (INTEL_INFO(dev_priv)->gen < 9) { > DRM_DEBUG("Unsupported tiling 0x%llx!\n", > mode_cmd->modifier[0]); > return -EINVAL; > @@ -14721,7 +14720,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_ARGB8888: > break; > case DRM_FORMAT_XRGB1555: > - if (INTEL_INFO(dev)->gen > 3) { > + if (INTEL_INFO(dev_priv)->gen > 3) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14729,7 +14728,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > break; > case DRM_FORMAT_ABGR8888: > if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && > - INTEL_INFO(dev)->gen < 9) { > + INTEL_INFO(dev_priv)->gen < 9) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14738,7 +14737,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_XBGR2101010: > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14755,7 +14754,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_UYVY: > case DRM_FORMAT_YVYU: > case DRM_FORMAT_VYUY: > - if (INTEL_INFO(dev)->gen < 5) { > + if (INTEL_INFO(dev_priv)->gen < 5) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -15320,7 +15319,7 @@ void intel_modeset_init(struct drm_device *dev) > > intel_init_pm(dev); > > - if (INTEL_INFO(dev)->num_pipes == 0) > + if (INTEL_INFO(dev_priv)->num_pipes == 0) > return; > > /* > @@ -15366,8 +15365,8 @@ void intel_modeset_init(struct drm_device *dev) > dev->mode_config.fb_base = ggtt->mappable_base; > > DRM_DEBUG_KMS("%d display pipe%s available.\n", > - INTEL_INFO(dev)->num_pipes, > - INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); > + INTEL_INFO(dev_priv)->num_pipes, > + INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); > > for_each_pipe(dev_priv, pipe) { > intel_crtc_init(dev, pipe); > @@ -15455,7 +15454,7 @@ intel_check_plane_mapping(struct intel_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 val; > > - if (INTEL_INFO(dev)->num_pipes == 1) > + if (INTEL_INFO(dev_priv)->num_pipes == 1) > return true; > > val = I915_READ(DSPCNTR(!crtc->plane)); > @@ -15522,7 +15521,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) > /* We need to sanitize the plane -> pipe mapping first because this will > * disable the crtc (and hence change the state) if it is wrong. Note > * that gen4+ has a fixed plane -> pipe mapping. */ > - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { > + if (INTEL_INFO(dev_priv)->gen < 4 && !intel_check_plane_mapping(crtc)) { > bool plane; > > DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", > @@ -16051,7 +16050,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, > int intel_modeset_vga_set_state(struct drm_device *dev, bool state) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; > + unsigned reg = INTEL_INFO(dev_priv)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; > u16 gmch_ctrl; > > if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { > @@ -16132,7 +16131,7 @@ intel_display_capture_error_state(struct drm_device *dev) > }; > int i; > > - if (INTEL_INFO(dev)->num_pipes == 0) > + if (INTEL_INFO(dev_priv)->num_pipes == 0) > return NULL; > > error = kzalloc(sizeof(*error), GFP_ATOMIC); > @@ -16155,13 +16154,13 @@ intel_display_capture_error_state(struct drm_device *dev) > > error->plane[i].control = I915_READ(DSPCNTR(i)); > error->plane[i].stride = I915_READ(DSPSTRIDE(i)); > - if (INTEL_INFO(dev)->gen <= 3) { > + if (INTEL_INFO(dev_priv)->gen <= 3) { > error->plane[i].size = I915_READ(DSPSIZE(i)); > error->plane[i].pos = I915_READ(DSPPOS(i)); > } > - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) > + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev)) > error->plane[i].addr = I915_READ(DSPADDR(i)); > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > error->plane[i].surface = I915_READ(DSPSURF(i)); > error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); > } > @@ -16173,7 +16172,7 @@ intel_display_capture_error_state(struct drm_device *dev) > } > > /* Note: this does not include DSI transcoders. */ > - error->num_transcoders = INTEL_INFO(dev)->num_pipes; > + error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; > if (HAS_DDI(dev_priv)) > error->num_transcoders++; /* Account for eDP. */ > > @@ -16213,7 +16212,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, > if (!error) > return; > > - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); > + err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); > if (IS_HASWELL(dev) || IS_BROADWELL(dev)) > err_printf(m, "PWR_WELL_CTL2: %08x\n", > error->power_well_driver); > @@ -16227,13 +16226,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, > err_printf(m, "Plane [%d]:\n", i); > err_printf(m, " CNTR: %08x\n", error->plane[i].control); > err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); > - if (INTEL_INFO(dev)->gen <= 3) { > + if (INTEL_INFO(dev_priv)->gen <= 3) { > err_printf(m, " SIZE: %08x\n", error->plane[i].size); > err_printf(m, " POS: %08x\n", error->plane[i].pos); > } > - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) > + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev)) > err_printf(m, " ADDR: %08x\n", error->plane[i].addr); > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > err_printf(m, " SURF: %08x\n", error->plane[i].surface); > err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); > } > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index da0c3d2..e2c565b 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1471,7 +1471,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > intel_fixed_panel_mode(intel_connector->panel.fixed_mode, > adjusted_mode); > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > int ret; > ret = skl_update_scaler_crtc(pipe_config); > if (ret) > @@ -3157,7 +3157,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) > > if (IS_BROXTON(dev)) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; > - else if (INTEL_INFO(dev)->gen >= 9) { > + else if (INTEL_INFO(dev_priv)->gen >= 9) { > if (dev_priv->vbt.edp.low_vswing && port == PORT_A) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; > return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; > @@ -3820,7 +3820,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) > DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > } > > - if (INTEL_INFO(dev)->gen >= 9 && > + if (INTEL_INFO(dev_priv)->gen >= 9 && > (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > uint8_t frame_sync_cap; > > @@ -5085,7 +5085,7 @@ bool intel_dp_is_edp(struct drm_device *dev, enum port port) > * eDP not supported on g4x. so bail out early just > * for a bit extra safety in case the VBT is bonkers. > */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_INFO(dev_priv)->gen < 5) > return false; > > if (port == PORT_A) > @@ -5399,7 +5399,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > return; > } > > - if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { > + if (INTEL_INFO(dev_priv)->gen >= 8 && !IS_CHERRYVIEW(dev)) { > switch (index) { > case DRRS_HIGH_RR: > intel_dp_set_m_n(intel_crtc, M1_N1); > @@ -5411,7 +5411,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > default: > DRM_ERROR("Unsupported refreshrate type\n"); > } > - } else if (INTEL_INFO(dev)->gen > 6) { > + } else if (INTEL_INFO(dev_priv)->gen > 6) { > i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); > u32 val; > > @@ -5688,7 +5688,7 @@ intel_dp_drrs_init(struct intel_connector *intel_connector, > INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); > mutex_init(&dev_priv->drrs.mutex); > > - if (INTEL_INFO(dev)->gen <= 6) { > + if (INTEL_INFO(dev_priv)->gen <= 6) { > DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); > return NULL; > } > @@ -5840,7 +5840,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > intel_dp->pps_pipe = INVALID_PIPE; > > /* intel_dp vfuncs */ > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; > else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) > intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; > @@ -5849,7 +5849,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, > else > intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; > else > intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; > @@ -6026,7 +6026,7 @@ intel_dp_init(struct drm_device *dev, > } else { > intel_encoder->pre_enable = g4x_pre_enable_dp; > intel_encoder->enable = g4x_enable_dp; > - if (INTEL_INFO(dev)->gen >= 5) > + if (INTEL_INFO(dev_priv)->gen >= 5) > intel_encoder->post_disable = ilk_post_disable_dp; > } > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 19efdd3..c7e970f 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -156,7 +156,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) > unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); > > /* PCH only available on ILK+ */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_INFO(dev_priv)->gen < 5) > return; > > if (pll == NULL) > diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c > index 79ac202..d4ccf35 100644 > --- a/drivers/gpu/drm/i915/intel_fbdev.c > +++ b/drivers/gpu/drm/i915/intel_fbdev.c > @@ -698,7 +698,7 @@ int intel_fbdev_init(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) > + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) > return -ENODEV; > > ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); > @@ -711,7 +711,7 @@ int intel_fbdev_init(struct drm_device *dev) > ifbdev->preferred_bpp = 32; > > ret = drm_fb_helper_init(dev, &ifbdev->helper, > - INTEL_INFO(dev)->num_pipes, 4); > + INTEL_INFO(dev_priv)->num_pipes, 4); > if (ret) { > kfree(ifbdev); > return ret; > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index a1db6a0..67b88de 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -2142,7 +2142,7 @@ static int logical_render_ring_init(struct drm_device *dev) > logical_ring_default_vfuncs(dev, engine); > > /* Override some for render ring. */ > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > engine->init_hw = gen9_init_render_ring; > else > engine->init_hw = gen8_init_render_ring; > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index 66e832b..6a5416a 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -123,7 +123,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, > pipe_config->base.adjusted_mode.flags |= flags; > > /* gen2/3 store dither state in pfit control, needs to match */ > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_INFO(dev_priv)->gen < 4) { > tmp = I915_READ(PFIT_CONTROL); > > pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; > @@ -186,7 +186,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) > /* Set the dithering flag on LVDS as needed, note that there is no > * special lvds dither control bit on pch-split platforms, dithering is > * only controlled through the PIPECONF reg. */ > - if (INTEL_INFO(dev)->gen == 4) { > + if (INTEL_INFO(dev_priv)->gen == 4) { > /* Bspec wording suggests that LVDS port dithering only exists > * for 18bpp panels. */ > if (crtc->config->dither && crtc->config->pipe_bpp == 18) > diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c > index 6694e92..a8c5269 100644 > --- a/drivers/gpu/drm/i915/intel_overlay.c > +++ b/drivers/gpu/drm/i915/intel_overlay.c > @@ -905,7 +905,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) > /* XXX: This is not the same logic as in the xorg driver, but more in > * line with the intel documentation for the i965 > */ > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > /* on i965 use the PGM reg to read out the autoscaler values */ > ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; > } else { > @@ -1069,7 +1069,7 @@ static int intel_panel_fitter_pipe(struct drm_device *dev) > u32 pfit_control; > > /* i830 doesn't have a panel fitter */ > - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > + if (INTEL_INFO(dev_priv)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > return -1; > > pfit_control = I915_READ(PFIT_CONTROL); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 43b24a1..e8e778f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2126,14 +2126,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) > wm[2] = (sskpd >> 12) & 0xFF; > wm[3] = (sskpd >> 20) & 0x1FF; > wm[4] = (sskpd >> 32) & 0x1FF; > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > uint32_t sskpd = I915_READ(MCH_SSKPD); > > wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; > wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; > wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; > wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; > - } else if (INTEL_INFO(dev)->gen >= 5) { > + } else if (INTEL_INFO(dev_priv)->gen >= 5) { > uint32_t mltr = I915_READ(MLTR_ILK); > > /* ILK primary LP0 latency is 700 ns */ > @@ -2338,7 +2338,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) > usable_level = max_level; > > /* ILK/SNB: LP2+ watermarks only w/o sprites */ > - if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled) > + if (INTEL_INFO(dev_priv)->gen <= 6 && pipe_wm->sprites_enabled) > usable_level = 1; > > /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ > @@ -2481,12 +2481,12 @@ static void ilk_wm_merge(struct drm_device *dev, > int last_enabled_level = max_level; > > /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ > - if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && > + if ((INTEL_INFO(dev_priv)->gen <= 6 || IS_IVYBRIDGE(dev)) && > config->num_pipes_active > 1) > return; > > /* ILK: FBC WM must be disabled always */ > - merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; > + merged->fbc_wm_enabled = INTEL_INFO(dev_priv)->gen >= 6; > > /* merge each WM1+ level */ > for (level = 1; level <= max_level; level++) { > @@ -2792,7 +2792,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, > previous->wm_lp_spr[0] != results->wm_lp_spr[0]) > I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); > > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_INFO(dev_priv)->gen >= 7) { > if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) > I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); > if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) > @@ -3733,7 +3733,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) > ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); > > /* 5/6 split only in single pipe config on IVB+ */ > - if (INTEL_INFO(dev)->gen >= 7 && > + if (INTEL_INFO(dev_priv)->gen >= 7 && > config.num_pipes_active == 1 && config.sprites_enabled) { > ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); > ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); > @@ -4102,7 +4102,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) > hw->wm_lp[2] = I915_READ(WM3_LP_ILK); > > hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_INFO(dev_priv)->gen >= 7) { > hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); > hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); > } > @@ -5140,7 +5140,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) > * No floor required for ring frequency on SKL. > */ > ring_freq = gpu_freq; > - } else if (INTEL_INFO(dev)->gen >= 8) { > + } else if (INTEL_INFO(dev_priv)->gen >= 8) { > /* max(2 * GT, DDR). NB: GT is 50MHz units */ > ring_freq = max(min_ring_freq, gpu_freq); > } else if (IS_HASWELL(dev)) { > @@ -5184,12 +5184,11 @@ void gen6_update_ring_freq(struct drm_device *dev) > > static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > u32 val, rp0; > > val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); > > - switch (INTEL_INFO(dev)->eu_total) { > + switch (INTEL_INFO(dev_priv)->eu_total) { > case 8: > /* (2 * 4) config */ > rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); > @@ -5791,10 +5790,9 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) > > unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > unsigned long val; > > - if (INTEL_INFO(dev)->gen != 5) > + if (INTEL_INFO(dev_priv)->gen != 5) > return 0; > > spin_lock_irq(&mchdev_lock); > @@ -5834,11 +5832,10 @@ static int _pxvid_to_vd(u8 pxvid) > > static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) > { > - struct drm_device *dev = dev_priv->dev; > const int vd = _pxvid_to_vd(pxvid); > const int vm = vd - 1125; > > - if (INTEL_INFO(dev)->is_mobile) > + if (INTEL_INFO(dev_priv)->is_mobile) > return vm > 0 ? vm : 0; > > return vd; > @@ -5879,9 +5876,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) > > void i915_update_gfx_val(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > - > - if (INTEL_INFO(dev)->gen != 5) > + if (INTEL_INFO(dev_priv)->gen != 5) > return; > > spin_lock_irq(&mchdev_lock); > @@ -5930,10 +5925,9 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) > > unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) > { > - struct drm_device *dev = dev_priv->dev; > unsigned long val; > > - if (INTEL_INFO(dev)->gen != 5) > + if (INTEL_INFO(dev_priv)->gen != 5) > return 0; > > spin_lock_irq(&mchdev_lock); > @@ -6246,7 +6240,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return; > > gen6_suspend_rps(dev); > @@ -6261,11 +6255,11 @@ void intel_disable_gt_powersave(struct drm_device *dev) > > if (IS_IRONLAKE_M(dev)) { > ironlake_disable_drps(dev); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > intel_suspend_gt_powersave(dev); > > mutex_lock(&dev_priv->rps.hw_lock); > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > gen9_disable_rps(dev); > else if (IS_CHERRYVIEW(dev)) > cherryview_disable_rps(dev); > @@ -6294,7 +6288,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) > cherryview_enable_rps(dev); > } else if (IS_VALLEYVIEW(dev)) { > valleyview_enable_rps(dev); > - } else if (INTEL_INFO(dev)->gen >= 9) { > + } else if (INTEL_INFO(dev_priv)->gen >= 9) { > gen9_enable_rc6(dev); > gen9_enable_rps(dev); > if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > @@ -6335,7 +6329,7 @@ void intel_enable_gt_powersave(struct drm_device *dev) > mutex_lock(&dev->struct_mutex); > intel_init_emon(dev); > mutex_unlock(&dev->struct_mutex); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > /* > * PCU communication is slow and this doesn't need to be > * done at any specific time, so do this out of our fast path > @@ -6358,7 +6352,7 @@ void intel_reset_gt_powersave(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_INFO(dev_priv)->gen < 6) > return; > > gen6_suspend_rps(dev); > @@ -7199,7 +7193,7 @@ void intel_init_pm(struct drm_device *dev) > i915_ironlake_get_mem_freq(dev); > > /* For FIFO watermark updates */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > skl_setup_wm_latency(dev); > dev_priv->display.update_wm = skl_update_wm; > } else if (HAS_PCH_SPLIT(dev)) { > @@ -7249,7 +7243,7 @@ void intel_init_pm(struct drm_device *dev) > dev_priv->display.update_wm = i9xx_update_wm; > dev_priv->display.get_fifo_size = i9xx_get_fifo_size; > } else if (IS_GEN2(dev)) { > - if (INTEL_INFO(dev)->num_pipes == 1) { > + if (INTEL_INFO(dev_priv)->num_pipes == 1) { > dev_priv->display.update_wm = i845_update_wm; > dev_priv->display.get_fifo_size = i845_get_fifo_size; > } else { > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index c3abae4..3205b03 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -204,7 +204,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) > I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), > intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_INFO(dev_priv)->gen >= 9) { > uint32_t val; > > val = I915_READ(aux_ctl_reg); > @@ -433,7 +433,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) > /* Enable PSR on the panel */ > hsw_psr_enable_sink(intel_dp); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_INFO(dev_priv)->gen >= 9) > intel_psr_activate(intel_dp); > } else { > vlv_psr_setup_vsc(intel_dp); > @@ -459,7 +459,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) > * - On HSW/BDW we get a recoverable frozen screen until next > * exit-activate sequence. > */ > - if (INTEL_INFO(dev)->gen < 9) > + if (INTEL_INFO(dev_priv)->gen < 9) > schedule_delayed_work(&dev_priv->psr.work, > msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 2e864b7..36fedea 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -509,7 +509,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > * arises: do we still need this and if so how should we go about > * invalidating the TLB? > */ > - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { > + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) { > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > /* ring should be idle before issuing a sync flush*/ > @@ -1215,7 +1215,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > return ret; > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > - if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) > + if (INTEL_INFO(dev_priv)->gen >= 4 && INTEL_INFO(dev_priv)->gen < 7) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > /* We need to disable the AsyncFlip performance optimisations in order > @@ -1224,12 +1224,12 @@ static int init_render_ring(struct intel_engine_cs *engine) > * > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > */ > - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) > + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > /* Required for the hardware to program scanline values for waiting */ > /* WaEnableFlushTlbInvalidationMode:snb */ > - if (INTEL_INFO(dev)->gen == 6) > + if (INTEL_INFO(dev_priv)->gen == 6) > I915_WRITE(GFX_MODE, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); > > @@ -1249,7 +1249,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > } > > - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) > + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > if (HAS_L3_DPF(dev)) > @@ -1283,7 +1283,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, > enum intel_engine_id id; > int ret, num_rings; > > - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); > + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); > num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; > #undef MBOX_UPDATE_DWORDS > > @@ -1325,7 +1325,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, > enum intel_engine_id id; > int ret, num_rings; > > - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); > + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); > num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; > #undef MBOX_UPDATE_DWORDS > > @@ -1365,7 +1365,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req, > int ret, num_rings; > > #define MBOX_UPDATE_DWORDS 3 > - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); > + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); > num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); > #undef MBOX_UPDATE_DWORDS > > @@ -2553,7 +2553,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) > struct drm_device *dev = engine->dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { > + if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > if (HAS_VEBOX(dev)) > @@ -2776,7 +2776,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > engine->exec_id = I915_EXEC_RENDER; > engine->mmio_base = RENDER_RING_BASE; > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > if (i915_semaphore_is_enabled(dev)) { > obj = i915_gem_alloc_object(dev, 4096); > if (obj == NULL) { > @@ -2808,11 +2808,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > engine->semaphore.signal = gen8_rcs_signal; > GEN8_RING_SEMAPHORE_INIT(engine); > } > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_INFO(dev_priv)->gen >= 6) { > engine->init_context = intel_rcs_ctx_init; > engine->add_request = gen6_add_request; > engine->flush = gen7_render_ring_flush; > - if (INTEL_INFO(dev)->gen == 6) > + if (INTEL_INFO(dev_priv)->gen == 6) > engine->flush = gen6_render_ring_flush; > engine->irq_get = gen6_ring_get_irq; > engine->irq_put = gen6_ring_put_irq; > @@ -2851,7 +2851,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; > } else { > engine->add_request = i9xx_add_request; > - if (INTEL_INFO(dev)->gen < 4) > + if (INTEL_INFO(dev_priv)->gen < 4) > engine->flush = gen2_render_ring_flush; > else > engine->flush = gen4_render_ring_flush; > @@ -2872,9 +2872,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; > else if (IS_GEN8(dev)) > engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; > - else if (INTEL_INFO(dev)->gen >= 6) > + else if (INTEL_INFO(dev_priv)->gen >= 6) > engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > - else if (INTEL_INFO(dev)->gen >= 4) > + else if (INTEL_INFO(dev_priv)->gen >= 4) > engine->dispatch_execbuffer = i965_dispatch_execbuffer; > else if (IS_I830(dev) || IS_845G(dev)) > engine->dispatch_execbuffer = i830_dispatch_execbuffer; > @@ -2906,7 +2906,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > if (ret) > return ret; > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_INFO(dev_priv)->gen >= 5) { > ret = intel_init_pipe_control(engine); > if (ret) > return ret; > @@ -2925,7 +2925,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > engine->exec_id = I915_EXEC_BSD; > > engine->write_tail = ring_write_tail; > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev_priv)->gen >= 6) { > engine->mmio_base = GEN6_BSD_RING_BASE; > /* gen6 bsd needs a special wa for tail updates */ > if (IS_GEN6(dev)) > @@ -2934,7 +2934,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > engine->add_request = gen6_add_request; > engine->get_seqno = gen6_ring_get_seqno; > engine->set_seqno = ring_set_seqno; > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > engine->irq_enable_mask = > GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; > engine->irq_get = gen8_ring_get_irq; > @@ -3038,7 +3038,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) > engine->add_request = gen6_add_request; > engine->get_seqno = gen6_ring_get_seqno; > engine->set_seqno = ring_set_seqno; > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > engine->irq_enable_mask = > GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; > engine->irq_get = gen8_ring_get_irq; > @@ -3097,7 +3097,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) > engine->get_seqno = gen6_ring_get_seqno; > engine->set_seqno = ring_set_seqno; > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_INFO(dev_priv)->gen >= 8) { > engine->irq_enable_mask = > GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; > engine->irq_get = gen8_ring_get_irq; > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c > index 2128fae..f12f879 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -1271,13 +1271,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > return; > > /* Set the SDVO control regs. */ > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > /* The real mode polarity is set by the SDVO commands, using > * struct intel_sdvo_dtd. */ > sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; > if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) > sdvox |= HDMI_COLOR_RANGE_16_235; > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_INFO(dev_priv)->gen < 5) > sdvox |= SDVO_BORDER_ENABLE; > } else { > sdvox = I915_READ(intel_sdvo->sdvo_reg); > @@ -1296,7 +1296,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > if (intel_sdvo->has_hdmi_audio) > sdvox |= SDVO_AUDIO_ENABLE; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_INFO(dev_priv)->gen >= 4) { > /* done in crtc_mode_set as the dpll_md reg must be written early */ > } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > /* done in crtc_mode_set as it lives inside the dpll register */ > @@ -1306,7 +1306,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > } > > if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && > - INTEL_INFO(dev)->gen < 5) > + INTEL_INFO(dev_priv)->gen < 5) > sdvox |= SDVO_STALL_SELECT; > intel_sdvo_write_sdvox(intel_sdvo, sdvox); > } > diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c > index 223129d..ead13ac 100644 > --- a/drivers/gpu/drm/i915/intel_tv.c > +++ b/drivers/gpu/drm/i915/intel_tv.c > @@ -1099,7 +1099,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder) > > set_color_conversion(dev_priv, color_conversion); > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_INFO(dev_priv)->gen >= 4) > I915_WRITE(TV_CLR_KNOBS, 0x00404000); > else > I915_WRITE(TV_CLR_KNOBS, 0x00606000); > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index ac2ac07..0ccefa9 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -315,7 +315,7 @@ static void intel_uncore_ellc_detect(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || > - INTEL_INFO(dev)->gen >= 9) && > + INTEL_INFO(dev_priv)->gen >= 9) && > (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { > /* The docs do not explain exactly how the calculation can be > * made. It is somewhat guessable, but for now, it's always > @@ -1259,7 +1259,7 @@ void intel_uncore_init(struct drm_device *dev) > > dev_priv->uncore.unclaimed_mmio_check = 1; > > - switch (INTEL_INFO(dev)->gen) { > + switch (INTEL_INFO(dev_priv)->gen) { > default: > case 9: > ASSIGN_WRITE_MMIO_VFUNCS(gen9); > @@ -1343,7 +1343,7 @@ int i915_reg_read_ioctl(struct drm_device *dev, > > for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { > if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && > - (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) > + (1 << INTEL_INFO(dev_priv)->gen & entry->gen_bitmask)) > break; > } >
On 08/04/16 07:09, Joonas Lahtinen wrote: > On to, 2016-04-07 at 18:57 +0100, Dave Gordon wrote: >> Where we have a suitable dev_priv pointer, we can use that rather than >> 'dev' for accessing INTEL_INFO(). This removes one level of memory >> reference, decreasing code size a little and possibly making everything >> a little faster. We could also do this for all the macros that implicitly >> use INTEL_INFO e.g. IS_CHERRYVIEW(). > > If applied to all macros, sounds like the right thing to do. Although, > I would prefer to see s/dev_priv/i915/g and then i915->info.gen, i915- >> info.is_cherryview etc. rather than dozens of macros. Maybe, but not all callsites actually have a 'dev_priv' in scope at present, which is why this had to be done with Coccinelle rather than just sed. I tried extending this to all IS_XXX() macros as well (but not as yet HAS_XXX()) and got: 36 files changed, 741 insertions(+), 763 deletions(-) the line count difference being due to 22 now-unused local variables deleted afterwards; the i915.ko binary shrank by about 2k - which represents quite a lot of instructions. So this isn't just a matter of style, like changing INTEL_INFO(dev)->gen with INTEL_GEN(dev), this transformation actually improves code size and presumably speed :) > It's going to cause a lot of rebasing, though. So depending on when we > apply dev_priv -> i915, might be or might not be worth the hassle now. > > Regards, Joonas The point of including the actual Cocci code in the commit message is that then anyone who has a set of not-yet-submitted changes can apply the Cocci script to their own codebase before attempting to rebase onto the new version of nightly, thus eliminating from the conflicts all those which are simply due to the patch applied to upstream. For this reason, I'd like to recommend that anyone doing this sort of bulk transformation with Cocci or awk or just sed should /always/ include the transformation script to help those with patches in flight. .Dave. >> Coccinelle: >> >> @dev_priv_param@ >> function FUNC; >> idexpression struct drm_device *DEV; >> identifier DEV_PRIV; >> @@ >> FUNC(..., struct drm_i915_private *DEV_PRIV, ...) >> { >> <... >> INTEL_INFO >> ( >> - DEV >> + DEV_PRIV >> ) >> ...> >> } >> >> @dev_priv_local@ >> idexpression struct drm_device *DEV; >> identifier DEV_PRIV; >> expression E; >> @@ >> { >> ... >> ( >> struct drm_i915_private *DEV_PRIV; >> | >> struct drm_i915_private *DEV_PRIV = E; >> ) >> <... >> INTEL_INFO >> ( >> - DEV >> + DEV_PRIV >> ) >> ...> >> } >> >> followed by manually deleting 6 now-unused "dev" locals. >> >> Signed-off-by: Dave Gordon <david.s.gordon@intel.com> >> --- >> drivers/gpu/drm/i915/i915_debugfs.c | 66 +++++++------- >> drivers/gpu/drm/i915/i915_dma.c | 30 +++--- >> drivers/gpu/drm/i915/i915_drv.c | 4 +- >> drivers/gpu/drm/i915/i915_gem.c | 6 +- >> drivers/gpu/drm/i915/i915_gem_context.c | 2 +- >> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +- >> drivers/gpu/drm/i915/i915_gem_fence.c | 8 +- >> drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +-- >> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- >> drivers/gpu/drm/i915/i915_gpu_error.c | 32 +++---- >> drivers/gpu/drm/i915/i915_irq.c | 36 ++++---- >> drivers/gpu/drm/i915/i915_suspend.c | 20 ++-- >> drivers/gpu/drm/i915/intel_color.c | 16 ++-- >> drivers/gpu/drm/i915/intel_crt.c | 6 +- >> drivers/gpu/drm/i915/intel_ddi.c | 4 +- >> drivers/gpu/drm/i915/intel_display.c | 141 ++++++++++++++--------------- >> drivers/gpu/drm/i915/intel_dp.c | 20 ++-- >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- >> drivers/gpu/drm/i915/intel_fbdev.c | 4 +- >> drivers/gpu/drm/i915/intel_lrc.c | 2 +- >> drivers/gpu/drm/i915/intel_lvds.c | 4 +- >> drivers/gpu/drm/i915/intel_overlay.c | 4 +- >> drivers/gpu/drm/i915/intel_pm.c | 50 +++++----- >> drivers/gpu/drm/i915/intel_psr.c | 6 +- >> drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++++---- >> drivers/gpu/drm/i915/intel_sdvo.c | 8 +- >> drivers/gpu/drm/i915/intel_tv.c | 2 +- >> drivers/gpu/drm/i915/intel_uncore.c | 6 +- >> 28 files changed, 270 insertions(+), 277 deletions(-)
On Mon, 11 Apr 2016, Dave Gordon <david.s.gordon@intel.com> wrote: > For this reason, I'd like to recommend that anyone doing this sort of > bulk transformation with Cocci or awk or just sed should /always/ > include the transformation script to help those with patches in flight. I think that's generally the expectation anyway for cocci changes. BR, Jani.
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index be4bcdc..d7f471b 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -612,7 +612,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) seq_puts(m, "Stall check waiting for page flip ioctl, "); seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); else addr = I915_READ(DSPADDR(crtc->plane)); @@ -809,7 +809,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GEN8_PCU_IIR)); seq_printf(m, "PCU interrupt enable:\t%08x\n", I915_READ(GEN8_PCU_IER)); - } else if (INTEL_INFO(dev)->gen >= 8) { + } else if (INTEL_INFO(dev_priv)->gen >= 8) { seq_printf(m, "Master Interrupt Control:\t%08x\n", I915_READ(GEN8_MASTER_IRQ)); @@ -935,7 +935,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GTIMR)); } for_each_engine(engine, dev_priv) { - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", engine->name, I915_READ_IMR(engine)); @@ -1172,7 +1172,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); mutex_unlock(&dev_priv->rps.hw_lock); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { u32 rp_state_limits; u32 gt_perf_status; u32 rp_state_cap; @@ -1680,7 +1680,7 @@ static int i915_fbc_fc_get(void *data, u64 *val) struct drm_device *dev = data; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) + if (INTEL_INFO(dev_priv)->gen < 7 || !HAS_FBC(dev)) return -ENODEV; *val = dev_priv->fbc.false_color; @@ -1694,7 +1694,7 @@ static int i915_fbc_fc_set(void *data, u64 val) struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) + if (INTEL_INFO(dev_priv)->gen < 7 || !HAS_FBC(dev)) return -ENODEV; mutex_lock(&dev_priv->fbc.lock); @@ -1730,7 +1730,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) seq_printf(m, "Enabled by kernel parameter: %s\n", yesno(i915.enable_ips)); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { seq_puts(m, "Currently: unknown\n"); } else { if (I915_READ(IPS_CTL) & IPS_ENABLE) @@ -2201,7 +2201,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ16(C0DRB3)); seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", I915_READ(MAD_DIMM_C0)); seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", @@ -2210,7 +2210,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ(MAD_DIMM_C2)); seq_printf(m, "TILECTL = 0x%08x\n", I915_READ(TILECTL)); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_INFO(dev_priv)->gen >= 8) seq_printf(m, "GAMTARBMODE = 0x%08x\n", I915_READ(GAMTARBMODE)); else @@ -2276,12 +2276,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *engine; - if (INTEL_INFO(dev)->gen == 6) + if (INTEL_INFO(dev_priv)->gen == 6) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); for_each_engine(engine, dev_priv) { seq_printf(m, "%s\n", engine->name); - if (INTEL_INFO(dev)->gen == 7) + if (INTEL_INFO(dev_priv)->gen == 7) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(engine))); seq_printf(m, "PP_DIR_BASE: 0x%08x\n", @@ -2315,9 +2315,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) return ret; intel_runtime_pm_get(dev_priv); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_INFO(dev_priv)->gen >= 8) gen8_ppgtt_info(m, dev); - else if (INTEL_INFO(dev)->gen >= 6) + else if (INTEL_INFO(dev_priv)->gen >= 6) gen6_ppgtt_info(m, dev); list_for_each_entry_reverse(file, &dev->filelist, lhead) { @@ -2669,7 +2669,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data) u64 power; u32 units; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -3137,7 +3137,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused) struct drm_device *dev = node->minor->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *engine; - int num_rings = hweight32(INTEL_INFO(dev)->ring_mask); + int num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); enum intel_engine_id id; int j, ret; @@ -3282,7 +3282,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) enum pipe pipe; int plane; - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_INFO(dev_priv)->gen < 9) return 0; drm_modeset_lock_all(dev); @@ -4034,7 +4034,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, if (IS_GEN2(dev)) ret = i8xx_pipe_crc_ctl_reg(&source, &val); - else if (INTEL_INFO(dev)->gen < 5) + else if (INTEL_INFO(dev_priv)->gen < 5) ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); @@ -4521,7 +4521,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.pri_latency; @@ -4537,7 +4537,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.spr_latency; @@ -4553,7 +4553,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.cur_latency; @@ -4644,7 +4644,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.pri_latency; @@ -4660,7 +4660,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.spr_latency; @@ -4676,7 +4676,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.cur_latency; @@ -4916,7 +4916,7 @@ i915_max_freq_get(void *data, u64 *val) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -4939,7 +4939,7 @@ i915_max_freq_set(void *data, u64 val) u32 hw_max, hw_min; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -4983,7 +4983,7 @@ i915_min_freq_get(void *data, u64 *val) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -5006,7 +5006,7 @@ i915_min_freq_set(void *data, u64 val) u32 hw_max, hw_min; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -5178,7 +5178,7 @@ static void gen9_sseu_device_status(struct drm_device *dev, stat->slice_total++; if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) - ss_cnt = INTEL_INFO(dev)->subslice_per_slice; + ss_cnt = INTEL_INFO(dev_priv)->subslice_per_slice; for (ss = 0; ss < ss_max; ss++) { unsigned int eu_cnt; @@ -5214,15 +5214,15 @@ static void broadwell_sseu_device_status(struct drm_device *dev, stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK); if (stat->slice_total) { - stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice; + stat->subslice_per_slice = INTEL_INFO(dev_priv)->subslice_per_slice; stat->subslice_total = stat->slice_total * stat->subslice_per_slice; - stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice; + stat->eu_per_subslice = INTEL_INFO(dev_priv)->eu_per_subslice; stat->eu_total = stat->eu_per_subslice * stat->subslice_total; /* subtract fused off EU(s) from enabled slice(s) */ for (s = 0; s < stat->slice_total; s++) { - u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s]; + u8 subslice_7eu = INTEL_INFO(dev_priv)->subslice_7eu[s]; stat->eu_total -= hweight8(subslice_7eu); } @@ -5284,7 +5284,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) struct drm_device *dev = inode->i_private; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return 0; intel_runtime_pm_get(dev_priv); @@ -5298,7 +5298,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) struct drm_device *dev = inode->i_private; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return 0; intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index b377753..fcdb1e0 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -165,7 +165,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_HAS_EXEC_CONSTANTS: - value = INTEL_INFO(dev)->gen >= 4; + value = INTEL_INFO(dev_priv)->gen >= 4; break; case I915_PARAM_HAS_RELAXED_DELTA: value = 1; @@ -213,12 +213,12 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_SUBSLICE_TOTAL: - value = INTEL_INFO(dev)->subslice_total; + value = INTEL_INFO(dev_priv)->subslice_total; if (!value) return -ENODEV; break; case I915_PARAM_EU_TOTAL: - value = INTEL_INFO(dev)->eu_total; + value = INTEL_INFO(dev_priv)->eu_total; if (!value) return -ENODEV; break; @@ -269,12 +269,12 @@ static int intel_alloc_mchbar_resource(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret; - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; @@ -301,7 +301,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) return ret; } - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); @@ -315,7 +315,7 @@ static void intel_setup_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool enabled; @@ -355,7 +355,7 @@ static void intel_teardown_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_INFO(dev_priv)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp; if (dev_priv->mchbar_need_disable) { @@ -479,7 +479,7 @@ static int i915_load_modeset_init(struct drm_device *dev) /* Always safe in the mode setting case. */ /* FIXME: do pre/post-mode set stuff in core KMS code */ dev->vblank_disable_allowed = true; - if (INTEL_INFO(dev)->num_pipes == 0) + if (INTEL_INFO(dev_priv)->num_pipes == 0) return 0; ret = intel_fbdev_init(dev); @@ -853,7 +853,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) DRM_INFO("Display disabled (module parameter)\n"); info->num_pipes = 0; } else if (info->num_pipes > 0 && - (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) && + (INTEL_INFO(dev_priv)->gen == 7 || INTEL_INFO(dev_priv)->gen == 8) && HAS_PCH_SPLIT(dev)) { u32 fuse_strap = I915_READ(FUSE_STRAP); u32 sfuse_strap = I915_READ(SFUSE_STRAP); @@ -877,7 +877,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) DRM_INFO("PipeC fused off\n"); info->num_pipes -= 1; } - } else if (info->num_pipes > 0 && INTEL_INFO(dev)->gen == 9) { + } else if (info->num_pipes > 0 && INTEL_INFO(dev_priv)->gen == 9) { u32 dfsm = I915_READ(SKL_DFSM); u8 disabled_mask = 0; bool invalid; @@ -915,7 +915,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) cherryview_sseu_info_init(dev); else if (IS_BROADWELL(dev)) broadwell_sseu_info_init(dev); - else if (INTEL_INFO(dev)->gen >= 9) + else if (INTEL_INFO(dev_priv)->gen >= 9) gen9_sseu_info_init(dev); /* Snooping is broken on BXT A stepping. */ @@ -1091,7 +1091,7 @@ static int i915_mmio_setup(struct drm_device *dev) * the register BAR remains the same size for all the earlier * generations up to Ironlake. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_INFO(dev_priv)->gen < 5) mmio_size = 512 * 1024; else mmio_size = 2 * 1024 * 1024; @@ -1373,8 +1373,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) * of the i915_driver_init_/i915_driver_register functions according * to the role/effect of the given init step. */ - if (INTEL_INFO(dev)->num_pipes) { - ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); + if (INTEL_INFO(dev_priv)->num_pipes) { + ret = drm_vblank_init(dev, INTEL_INFO(dev_priv)->num_pipes); if (ret) goto out_cleanup_hw; } diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 29b4e79..d50de67 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -458,7 +458,7 @@ void intel_detect_pch(struct drm_device *dev) /* In all current cases, num_pipes is equivalent to the PCH_NOP setting * (which really amounts to a PCH but no South Display). */ - if (INTEL_INFO(dev)->num_pipes == 0) { + if (INTEL_INFO(dev_priv)->num_pipes == 0) { dev_priv->pch_type = PCH_NOP; return; } @@ -949,7 +949,7 @@ int i915_reset(struct drm_device *dev) * previous concerns that it doesn't respond well to some forms * of re-init after reset. */ - if (INTEL_INFO(dev)->gen > 5) + if (INTEL_INFO(dev_priv)->gen > 5) intel_enable_gt_powersave(dev); return 0; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b342f67..9d13a70 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4730,7 +4730,7 @@ void i915_gem_init_swizzling(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 5 || + if (INTEL_INFO(dev_priv)->gen < 5 || dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; @@ -4832,7 +4832,7 @@ i915_gem_init_hw(struct drm_device *dev) struct intel_engine_cs *engine; int ret, j; - if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) + if (INTEL_INFO(dev_priv)->gen < 6 && !intel_enable_gtt()) return -EIO; /* Double layer security blanket, see i915_gem_init() */ @@ -4850,7 +4850,7 @@ i915_gem_init_hw(struct drm_device *dev) u32 temp = I915_READ(GEN7_MSG_CTL); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); I915_WRITE(GEN7_MSG_CTL, temp); - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_INFO(dev_priv)->gen >= 7) { u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); temp &= ~RESET_PCH_HANDSHAKE_ENABLE; I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index fe580cb..92ae104 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -111,7 +111,7 @@ static int get_context_size(struct drm_device *dev) int ret; u32 reg; - switch (INTEL_INFO(dev)->gen) { + switch (INTEL_INFO(dev_priv)->gen) { case 6: reg = I915_READ(CXT_SIZE); ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 0ee61fd..cd6a25c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -335,7 +335,7 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj, offset & PAGE_MASK); iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { offset += sizeof(uint32_t); if (offset_in_page(offset) == 0) { @@ -1264,19 +1264,19 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, } if (instp_mode != dev_priv->relative_constants_mode) { - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { DRM_DEBUG("no rel constants on pre-gen4\n"); return -EINVAL; } - if (INTEL_INFO(dev)->gen > 5 && + if (INTEL_INFO(dev_priv)->gen > 5 && instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); return -EINVAL; } /* The HW changed the meaning on this bit on gen6 */ - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev_priv)->gen >= 6) instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; } break; diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c index a2b938e..b8c810f 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence.c @@ -62,7 +62,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg, i915_reg_t fence_reg_lo, fence_reg_hi; int fence_pitch_shift; - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { fence_reg_lo = FENCE_REG_GEN6_LO(reg); fence_reg_hi = FENCE_REG_GEN6_HI(reg); fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; @@ -209,7 +209,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, i830_write_fence_reg(dev, reg, obj); else if (IS_GEN3(dev)) i915_write_fence_reg(dev, reg, obj); - else if (INTEL_INFO(dev)->gen >= 4) + else if (INTEL_INFO(dev_priv)->gen >= 4) i965_write_fence_reg(dev, reg, obj); /* And similarly be paranoid that no direct access to this region @@ -553,7 +553,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { + if (INTEL_INFO(dev_priv)->gen >= 8 || IS_VALLEYVIEW(dev)) { /* * On BDW+, swizzling is not used. We leave the CPU memory * controller in charge of optimizing memory accesses without @@ -563,7 +563,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { if (dev_priv->preserve_bios_swizzle) { if (I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index da6e3a5..59aefbd 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2281,7 +2281,7 @@ void i915_check_and_clear_faults(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_engine_cs *engine; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return; for_each_engine(engine, dev_priv) { @@ -2322,7 +2322,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) /* Don't bother messing with faults pre GEN6 as we have little * documentation supporting that it's a good idea. */ - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return; i915_check_and_clear_faults(dev); @@ -3050,7 +3050,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); } else if (IS_CHERRYVIEW(dev)) { @@ -3166,10 +3166,10 @@ int i915_ggtt_init_hw(struct drm_device *dev) struct i915_ggtt *ggtt = &dev_priv->ggtt; int ret; - if (INTEL_INFO(dev)->gen <= 5) { + if (INTEL_INFO(dev_priv)->gen <= 5) { ggtt->probe = i915_gmch_probe; ggtt->base.cleanup = i915_gmch_remove; - } else if (INTEL_INFO(dev)->gen < 8) { + } else if (INTEL_INFO(dev_priv)->gen < 8) { ggtt->probe = gen6_gmch_probe; ggtt->base.cleanup = gen6_gmch_remove; if (IS_HASWELL(dev) && dev_priv->ellc_size) @@ -3178,7 +3178,7 @@ int i915_ggtt_init_hw(struct drm_device *dev) ggtt->base.pte_encode = hsw_pte_encode; else if (IS_VALLEYVIEW(dev)) ggtt->base.pte_encode = byt_pte_encode; - else if (INTEL_INFO(dev)->gen >= 7) + else if (INTEL_INFO(dev_priv)->gen >= 7) ggtt->base.pte_encode = ivb_pte_encode; else ggtt->base.pte_encode = snb_pte_encode; @@ -3267,7 +3267,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) i915_gem_clflush_object(obj, obj->pin_display); } - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) chv_setup_private_ppat(dev_priv); else diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index ea06da0..fe1e5f4 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -106,7 +106,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) * */ base = 0; - if (INTEL_INFO(dev)->gen >= 3) { + if (INTEL_INFO(dev_priv)->gen >= 3) { /* Read Graphics Base of Stolen Memory directly */ pci_read_config_dword(dev->pdev, 0x5c, &base); base &= ~((1<<20) - 1); @@ -188,7 +188,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) return 0; /* make sure we don't clobber the GTT if it's within stolen memory */ - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { + if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { struct { u32 start, end; } stolen[2] = { @@ -401,7 +401,7 @@ int i915_gem_init_stolen(struct drm_device *dev) mutex_init(&dev_priv->mm.stolen_lock); #ifdef CONFIG_INTEL_IOMMU - if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { + if (intel_iommu_gfx_mapped && INTEL_INFO(dev_priv)->gen < 8) { DRM_INFO("DMAR active, disabling use of stolen memory\n"); return 0; } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 6d63a2f..fa7aaf7 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -381,7 +381,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "EIR: 0x%08x\n", error->eir); err_printf(m, "IER: 0x%08x\n", error->ier); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { for (i = 0; i < 4; i++) err_printf(m, "GTIER gt %d: 0x%08x\n", i, error->gtier[i]); @@ -400,17 +400,17 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { err_printf(m, "ERROR: 0x%08x\n", error->error); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_INFO(dev_priv)->gen >= 8) err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", error->fault_data1, error->fault_data0); err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); } - if (INTEL_INFO(dev)->gen == 7) + if (INTEL_INFO(dev_priv)->gen == 7) err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); for (i = 0; i < ARRAY_SIZE(error->ring); i++) @@ -835,7 +835,7 @@ static void i915_gem_record_fences(struct drm_device *dev, } else if (IS_GEN5(dev) || IS_GEN4(dev)) { for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); } @@ -899,24 +899,24 @@ static void i915_record_ring_state(struct drm_device *dev, { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { ering->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); ering->fault_reg = I915_READ(RING_FAULT_REG(engine)); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_INFO(dev_priv)->gen >= 8) gen8_record_semaphore_state(dev_priv, error, engine, ering); else gen6_record_semaphore_state(dev_priv, engine, ering); } - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { ering->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); ering->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); ering->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); ering->instdone = I915_READ(RING_INSTDONE(engine->mmio_base)); ering->instps = I915_READ(RING_INSTPS(engine->mmio_base)); ering->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; } @@ -980,7 +980,7 @@ static void i915_record_ring_state(struct drm_device *dev, else if (IS_GEN7(dev)) ering->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE(engine)); - else if (INTEL_INFO(dev)->gen >= 8) + else if (INTEL_INFO(dev_priv)->gen >= 8) for (i = 0; i < 4; i++) { ering->vm_info.pdp[i] = I915_READ(GEN8_RING_PDP_UDW(engine, i)); @@ -1253,7 +1253,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (IS_GEN7(dev)) error->err_int = I915_READ(GEN7_ERR_INT); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } @@ -1265,10 +1265,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, } /* 2: Registers which belong to multiple generations */ - if (INTEL_INFO(dev)->gen >= 7) + if (INTEL_INFO(dev_priv)->gen >= 7) error->forcewake = I915_READ_FW(FORCEWAKE_MT); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { error->derrmr = I915_READ(DERRMR); error->error = I915_READ(ERROR_GEN6); error->done_reg = I915_READ(DONE_REG); @@ -1284,7 +1284,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (HAS_HW_CONTEXTS(dev)) error->ccid = I915_READ(CCID); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { error->ier = I915_READ(GEN8_DE_MISC_IER); for (i = 0; i < 4; i++) error->gtier[i] = I915_READ(GEN8_GT_IER(i)); @@ -1315,7 +1315,7 @@ static void i915_error_capture_msg(struct drm_device *dev, len = scnprintf(error->error_msg, sizeof(error->error_msg), "GPU HANG: ecode %d:%d:0x%08x", - INTEL_INFO(dev)->gen, ring_id, ecode); + INTEL_INFO(dev_priv)->gen, ring_id, ecode); if (ring_id != -1 && error->ring[ring_id].pid != -1) len += scnprintf(error->error_msg + len, @@ -1458,7 +1458,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); instdone[1] = I915_READ(GEN4_INSTDONE1); - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_INFO(dev_priv)->gen >= 7) { instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); instdone[1] = I915_READ(GEN7_SC_INSTDONE); instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index c36aa64..3994c89a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -617,7 +617,7 @@ static void i915_enable_asle_pipestat(struct drm_device *dev) spin_lock_irq(&dev_priv->irq_lock); i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) i915_enable_pipestat(dev_priv, PIPE_A, PIPE_LEGACY_BLC_EVENT_STATUS); @@ -835,7 +835,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, if (stime) *stime = ktime_get(); - if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { + if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev_priv)->gen >= 5) { /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. */ @@ -897,7 +897,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, else position += vtotal - vbl_end; - if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { + if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev_priv)->gen >= 5) { *vpos = position; *hpos = 0; } else { @@ -1591,12 +1591,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) struct drm_i915_private *dev_priv = dev->dev_private; uint32_t res1, res2; - if (INTEL_INFO(dev)->gen >= 3) + if (INTEL_INFO(dev_priv)->gen >= 3) res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); else res1 = 0; - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); else res2 = 0; @@ -2215,7 +2215,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) if (gt_iir) { I915_WRITE(GTIIR, gt_iir); ret = IRQ_HANDLED; - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev_priv)->gen >= 6) snb_gt_irq_handler(dev, dev_priv, gt_iir); else ilk_gt_irq_handler(dev, dev_priv, gt_iir); @@ -2225,13 +2225,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) if (de_iir) { I915_WRITE(DEIIR, de_iir); ret = IRQ_HANDLED; - if (INTEL_INFO(dev)->gen >= 7) + if (INTEL_INFO(dev_priv)->gen >= 7) ivb_display_irq_handler(dev, de_iir); else ilk_display_irq_handler(dev, de_iir); } - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { u32 pm_iir = I915_READ(GEN6_PMIIR); if (pm_iir) { I915_WRITE(GEN6_PMIIR, pm_iir); @@ -2614,7 +2614,7 @@ static void i915_report_and_clear_eir(struct drm_device *dev) pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); for (i = 0; i < ARRAY_SIZE(instdone); i++) pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { u32 ipeir = I915_READ(IPEIR); pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); @@ -2704,7 +2704,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) unsigned long irqflags; spin_lock_irqsave(&dev_priv->irq_lock, irqflags); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) i915_enable_pipestat(dev_priv, pipe, PIPE_START_VBLANK_INTERRUPT_STATUS); else @@ -2719,7 +2719,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : + uint32_t bit = (INTEL_INFO(dev_priv)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -2773,7 +2773,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : + uint32_t bit = (INTEL_INFO(dev_priv)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -3036,7 +3036,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd) return HANGCHECK_KICK; } - if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { + if (INTEL_INFO(dev_priv)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { switch (semaphore_passed(engine)) { default: return HANGCHECK_HUNG; @@ -3257,7 +3257,7 @@ static void gen5_gt_irq_reset(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; GEN5_IRQ_RESET(GT); - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev_priv)->gen >= 6) GEN5_IRQ_RESET(GEN6_PM); } @@ -3457,12 +3457,12 @@ static void ilk_hpd_irq_setup(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; u32 hotplug_irqs, hotplug, enabled_irqs; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_INFO(dev_priv)->gen >= 7) { hotplug_irqs = DE_DP_A_HOTPLUG_IVB; enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); @@ -3564,7 +3564,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { /* * RPS interrupts will get enabled/disabled on demand when RPS * itself is enabled/disabled. @@ -3582,7 +3582,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; u32 display_mask, extra_mask; - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_INFO(dev_priv)->gen >= 7) { display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | DE_PLANEB_FLIP_DONE_IVB | diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 34e061a..34c9ed4 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -34,13 +34,13 @@ static void i915_save_display(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* Display arbitration control */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_INFO(dev_priv)->gen <= 4) dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); /* LVDS state */ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) + else if (INTEL_INFO(dev_priv)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) dev_priv->regfile.saveLVDS = I915_READ(LVDS); /* Panel power sequencer */ @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev) dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); - } else if (INTEL_INFO(dev)->gen <= 4) { + } else if (INTEL_INFO(dev_priv)->gen <= 4) { dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); @@ -57,7 +57,7 @@ static void i915_save_display(struct drm_device *dev) } /* save FBC interval */ - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev)) dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); } @@ -67,7 +67,7 @@ static void i915_restore_display(struct drm_device *dev) u32 mask = 0xffffffff; /* Display arbitration */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_INFO(dev_priv)->gen <= 4) I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); mask = ~LVDS_PORT_EN; @@ -75,7 +75,7 @@ static void i915_restore_display(struct drm_device *dev) /* LVDS state */ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) + else if (INTEL_INFO(dev_priv)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); /* Panel power sequencer */ @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); - } else if (INTEL_INFO(dev)->gen <= 4) { + } else if (INTEL_INFO(dev_priv)->gen <= 4) { I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); @@ -95,7 +95,7 @@ static void i915_restore_display(struct drm_device *dev) intel_fbc_global_disable(dev_priv); /* restore FBC interval */ - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev)) I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); i915_redisable_vga(dev); @@ -115,7 +115,7 @@ int i915_save_state(struct drm_device *dev) &dev_priv->regfile.saveGCDGMBUS); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_INFO(dev_priv)->gen < 7) dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ @@ -161,7 +161,7 @@ int i915_restore_state(struct drm_device *dev) i915_restore_display(dev); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_INFO(dev_priv)->gen < 7) I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 1b3f974..8e34020 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -179,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); - if (INTEL_INFO(dev)->gen > 6) { + if (INTEL_INFO(dev_priv)->gen > 6) { uint16_t postoff = 0; if (intel_crtc->config->limited_color_range) @@ -346,7 +346,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crtc_state *intel_state = to_intel_crtc_state(state); enum pipe pipe = to_intel_crtc(crtc)->pipe; - uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size; + uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; if (crtc_state_is_legacy(state)) { haswell_load_luts(state); @@ -442,7 +442,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) if (state->degamma_lut) { lut = (struct drm_color_lut *) state->degamma_lut->data; - lut_size = INTEL_INFO(dev)->color.degamma_lut_size; + lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; for (i = 0; i < lut_size; i++) { /* Write LUT in U0.14 format. */ word0 = @@ -457,7 +457,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state) if (state->gamma_lut) { lut = (struct drm_color_lut *) state->gamma_lut->data; - lut_size = INTEL_INFO(dev)->color.gamma_lut_size; + lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; for (i = 0; i < lut_size; i++) { /* Write LUT in U0.10 format. */ word0 = @@ -545,9 +545,9 @@ void intel_color_init(struct drm_crtc *crtc) } /* Enable color management support when we have degamma & gamma LUTs. */ - if (INTEL_INFO(dev)->color.degamma_lut_size != 0 && - INTEL_INFO(dev)->color.gamma_lut_size != 0) + if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 && + INTEL_INFO(dev_priv)->color.gamma_lut_size != 0) drm_helper_crtc_enable_color_mgmt(crtc, - INTEL_INFO(dev)->color.degamma_lut_size, - INTEL_INFO(dev)->color.gamma_lut_size); + INTEL_INFO(dev_priv)->color.degamma_lut_size, + INTEL_INFO(dev_priv)->color.gamma_lut_size); } diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index a2a31fd..bdc15a9 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -152,7 +152,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; u32 adpa; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_INFO(dev_priv)->gen >= 5) adpa = ADPA_HOTPLUG_BITS; else adpa = 0; @@ -647,7 +647,7 @@ intel_crt_detect(struct drm_connector *connector, bool force) if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { if (intel_crt_detect_ddc(connector)) status = connector_status_connected; - else if (INTEL_INFO(dev)->gen < 4) + else if (INTEL_INFO(dev_priv)->gen < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); else if (i915.load_detect_test) @@ -713,7 +713,7 @@ static void intel_crt_reset(struct drm_connector *connector) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crt *crt = intel_attached_crt(connector); - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_INFO(dev_priv)->gen >= 5) { u32 adpa; adpa = I915_READ(crt->adpa_reg); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 921edf1..a633155 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1657,7 +1657,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); - else if (INTEL_INFO(dev)->gen < 9) + else if (INTEL_INFO(dev_priv)->gen < 9) I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } @@ -1685,7 +1685,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) } else if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - if (port == PORT_A && INTEL_INFO(dev)->gen < 9) + if (port == PORT_A && INTEL_INFO(dev_priv)->gen < 9) intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index feb7028..9420637 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1116,7 +1116,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { i915_reg_t reg = PIPECONF(cpu_transcoder); /* Wait for the Pipe State to go off */ @@ -1334,11 +1334,10 @@ static void assert_plane(struct drm_i915_private *dev_priv, static void assert_planes_disabled(struct drm_i915_private *dev_priv, enum pipe pipe) { - struct drm_device *dev = dev_priv->dev; int i; /* Primary planes are fixed to pipes on gen4+ */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { u32 val = I915_READ(DSPCNTR(pipe)); I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, "plane %c assertion failure, should be disabled but not\n", @@ -1363,7 +1362,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, struct drm_device *dev = dev_priv->dev; int sprite; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { for_each_sprite(dev_priv, pipe, sprite) { u32 val = I915_READ(PLANE_CTL(pipe, sprite)); I915_STATE_WARN(val & PLANE_CTL_ENABLE, @@ -1377,12 +1376,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, "sprite %c assertion failure, should be off on pipe %c but is still active\n", sprite_name(pipe, sprite), pipe_name(pipe)); } - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_INFO(dev_priv)->gen >= 7) { u32 val = I915_READ(SPRCTL(pipe)); I915_STATE_WARN(val & SPRITE_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", plane_name(pipe), pipe_name(pipe)); - } else if (INTEL_INFO(dev)->gen >= 5) { + } else if (INTEL_INFO(dev_priv)->gen >= 5) { u32 val = I915_READ(DVSCNTR(pipe)); I915_STATE_WARN(val & DVS_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", @@ -1664,7 +1663,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) POSTING_READ(reg); udelay(150); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { I915_WRITE(DPLL_MD(crtc->pipe), crtc->config->dpll_hw_state.dpll_md); } else { @@ -2639,7 +2638,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, dspcntr |= DISPLAY_PLANE_ENABLE; - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { if (intel_crtc->pipe == PIPE_B) dspcntr |= DISPPLANE_SEL_PIPE_B; @@ -2684,7 +2683,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, BUG(); } - if (INTEL_INFO(dev)->gen >= 4 && + if (INTEL_INFO(dev_priv)->gen >= 4 && obj->tiling_mode != I915_TILING_NONE) dspcntr |= DISPPLANE_TILED; @@ -2693,7 +2692,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, linear_offset = y * fb->pitches[0] + x * cpp; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { intel_crtc->dspaddr_offset = intel_compute_tile_offset(&x, &y, fb, 0, fb->pitches[0], rotation); @@ -2721,7 +2720,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, I915_WRITE(reg, dspcntr); I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { I915_WRITE(DSPSURF(plane), i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); @@ -3160,7 +3159,7 @@ void intel_finish_reset(struct drm_device *dev) return; /* reset doesn't touch the display */ - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) { /* * Flips in the rings have been nuked by the reset, * so update the base address of all primary @@ -3242,7 +3241,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, (pipe_config->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { skl_detach_scalers(crtc); if (pipe_config->pch_pfit.enabled) @@ -4870,7 +4869,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (!intel_crtc->config->has_dsi_encoder) intel_ddi_enable_pipe_clock(intel_crtc); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) skylake_pfit_enable(intel_crtc); else ironlake_pfit_enable(intel_crtc); @@ -5035,7 +5034,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->config->has_dsi_encoder) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(intel_crtc, false); @@ -6543,7 +6542,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; /* FIXME should check pixel clock limits on all platforms */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; /* @@ -6577,7 +6576,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && + if ((INTEL_INFO(dev_priv)->gen > 4 || IS_G4X(dev)) && adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) return -EINVAL; @@ -7119,7 +7118,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, int pipe = crtc->pipe; enum transcoder transcoder = crtc->config->cpu_transcoder; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_INFO(dev_priv)->gen >= 5) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); @@ -7128,7 +7127,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, * for gen < 8) and if DRRS is supported (to make sure the * registers are not unnecessarily accessed). */ - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev_priv)->gen < 8) && crtc->config->has_drrs) { I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); @@ -7501,7 +7500,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -7515,7 +7514,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLL_VCO_ENABLE; crtc_state->dpll_hw_state.dpll = dpll; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { u32 dpll_md = (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc_state->dpll_hw_state.dpll_md = dpll_md; @@ -7588,7 +7587,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) vsyncshift += adjusted_mode->crtc_htotal; } - if (INTEL_INFO(dev)->gen > 3) + if (INTEL_INFO(dev_priv)->gen > 3) I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); I915_WRITE(HTOTAL(cpu_transcoder), @@ -7757,7 +7756,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (INTEL_INFO(dev)->gen < 4 || + if (INTEL_INFO(dev_priv)->gen < 4 || intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; else @@ -7975,7 +7974,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; uint32_t tmp; - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) + if (INTEL_INFO(dev_priv)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) return; tmp = I915_READ(PFIT_CONTROL); @@ -7983,7 +7982,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, return; /* Check whether the pfit is attached to our pipe. */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { if (crtc->pipe != PIPE_B) return; } else { @@ -7993,7 +7992,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, pipe_config->gmch_pfit.control = tmp; pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_INFO(dev_priv)->gen < 5) pipe_config->gmch_pfit.lvds_border_bits = I915_READ(LVDS) & LVDS_BORDER_ENABLE; } @@ -8050,7 +8049,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier[0] = I915_FORMAT_MOD_X_TILED; @@ -8062,7 +8061,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(plane)); else @@ -8166,7 +8165,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_INFO(dev_priv)->gen < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; intel_get_pipe_timings(crtc, pipe_config); @@ -8174,7 +8173,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { /* No way to read it out on pipes B and C */ if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; @@ -8954,7 +8953,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_INFO(dev_priv)->gen >= 5) { m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) @@ -8966,7 +8965,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, * gen < 8) and if DRRS is supported (to make sure the * registers are not unnecessarily read). */ - if (m2_n2 && INTEL_INFO(dev)->gen < 8 && + if (m2_n2 && INTEL_INFO(dev_priv)->gen < 8 && crtc->config->has_drrs) { m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); @@ -9168,7 +9167,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier[0] = I915_FORMAT_MOD_X_TILED; @@ -9934,7 +9933,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - if (INTEL_INFO(dev)->gen < 9 && + if (INTEL_INFO(dev_priv)->gen < 9 && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -9985,11 +9984,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { skl_init_scalers(dev, crtc, pipe_config); } - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { pipe_config->scaler_state.scaler_id = -1; pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); } @@ -9997,7 +9996,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT(power_domain); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -10779,7 +10778,7 @@ void intel_mark_busy(struct drm_device *dev) intel_runtime_pm_get(dev_priv); i915_update_gfx_val(dev_priv); - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev_priv)->gen >= 6) gen6_rps_busy(dev_priv); dev_priv->mm.busy = true; } @@ -10793,7 +10792,7 @@ void intel_mark_idle(struct drm_device *dev) dev_priv->mm.busy = false; - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_INFO(dev_priv)->gen >= 6) gen6_rps_idle(dev->dev_private); intel_runtime_pm_put(dev_priv); @@ -10915,7 +10914,7 @@ static bool page_flip_finished(struct intel_crtc *crtc) * really needed there. But since ctg has the registers, * include it in the check anyway. */ - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) + if (INTEL_INFO(dev_priv)->gen < 5 && !IS_G4X(dev)) return true; /* @@ -11436,7 +11435,7 @@ static bool __intel_pageflip_stall_check(struct drm_device *dev, /* Potential stall - if we see that the flip has happened, * assume a missed interrupt. */ - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); else addr = I915_READ(DSPADDR(intel_crtc->plane)); @@ -11508,7 +11507,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. */ - if (INTEL_INFO(dev)->gen > 3 && + if (INTEL_INFO(dev_priv)->gen > 3 && (fb->offsets[0] != crtc->primary->fb->offsets[0] || fb->pitches[0] != crtc->primary->fb->pitches[0])) return -EINVAL; @@ -11570,7 +11569,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, atomic_inc(&intel_crtc->unpin_work_count); intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) + if (INTEL_INFO(dev_priv)->gen >= 5 || IS_G4X(dev)) work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { @@ -11580,7 +11579,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, engine = NULL; } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { engine = &dev_priv->engine[BCS]; - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_INFO(dev_priv)->gen >= 7) { engine = i915_gem_request_get_engine(obj->last_write_req); if (engine == NULL || engine->id != RCS) engine = &dev_priv->engine[BCS]; @@ -11774,7 +11773,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, bool turn_off, turn_on, visible, was_visible; struct drm_framebuffer *fb = plane_state->fb; - if (crtc_state && INTEL_INFO(dev)->gen >= 9 && + if (crtc_state && INTEL_INFO(dev_priv)->gen >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { ret = skl_update_scaler_plane( to_intel_crtc_state(crtc_state), @@ -11833,7 +11832,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, /* Pre-gen9 platforms need two-step watermark updates */ if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) + INTEL_INFO(dev_priv)->gen < 9 && dev_priv->display.optimize_watermarks) to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; if (visible || was_visible) @@ -11966,7 +11965,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, } } - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -12763,7 +12762,7 @@ static void check_wm_state(struct drm_device *dev) struct intel_crtc *intel_crtc; int plane; - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_INFO(dev_priv)->gen < 9) return; skl_ddb_get_hw_state(dev_priv, &hw_ddb); @@ -14238,7 +14237,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) crtc_state->base.crtc = &intel_crtc->base; /* initialize shared scalers */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { if (pipe == PIPE_C) intel_crtc->num_scalers = 1; else @@ -14266,7 +14265,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) */ intel_crtc->pipe = pipe; intel_crtc->plane = pipe; - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { + if (HAS_FBC(dev) && INTEL_INFO(dev_priv)->gen < 4) { DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); intel_crtc->plane = !pipe; } @@ -14368,7 +14367,7 @@ static bool intel_crt_present(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) return false; if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) @@ -14673,7 +14672,7 @@ static int intel_framebuffer_init(struct drm_device *dev, switch (mode_cmd->modifier[0]) { case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: - if (INTEL_INFO(dev)->gen < 9) { + if (INTEL_INFO(dev_priv)->gen < 9) { DRM_DEBUG("Unsupported tiling 0x%llx!\n", mode_cmd->modifier[0]); return -EINVAL; @@ -14721,7 +14720,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - if (INTEL_INFO(dev)->gen > 3) { + if (INTEL_INFO(dev_priv)->gen > 3) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14729,7 +14728,7 @@ static int intel_framebuffer_init(struct drm_device *dev, break; case DRM_FORMAT_ABGR8888: if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && - INTEL_INFO(dev)->gen < 9) { + INTEL_INFO(dev_priv)->gen < 9) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14738,7 +14737,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14755,7 +14754,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: - if (INTEL_INFO(dev)->gen < 5) { + if (INTEL_INFO(dev_priv)->gen < 5) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -15320,7 +15319,7 @@ void intel_modeset_init(struct drm_device *dev) intel_init_pm(dev); - if (INTEL_INFO(dev)->num_pipes == 0) + if (INTEL_INFO(dev_priv)->num_pipes == 0) return; /* @@ -15366,8 +15365,8 @@ void intel_modeset_init(struct drm_device *dev) dev->mode_config.fb_base = ggtt->mappable_base; DRM_DEBUG_KMS("%d display pipe%s available.\n", - INTEL_INFO(dev)->num_pipes, - INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); + INTEL_INFO(dev_priv)->num_pipes, + INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); for_each_pipe(dev_priv, pipe) { intel_crtc_init(dev, pipe); @@ -15455,7 +15454,7 @@ intel_check_plane_mapping(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = dev->dev_private; u32 val; - if (INTEL_INFO(dev)->num_pipes == 1) + if (INTEL_INFO(dev_priv)->num_pipes == 1) return true; val = I915_READ(DSPCNTR(!crtc->plane)); @@ -15522,7 +15521,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. Note * that gen4+ has a fixed plane -> pipe mapping. */ - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { + if (INTEL_INFO(dev_priv)->gen < 4 && !intel_check_plane_mapping(crtc)) { bool plane; DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", @@ -16051,7 +16050,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, int intel_modeset_vga_set_state(struct drm_device *dev, bool state) { struct drm_i915_private *dev_priv = dev->dev_private; - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; + unsigned reg = INTEL_INFO(dev_priv)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; u16 gmch_ctrl; if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { @@ -16132,7 +16131,7 @@ intel_display_capture_error_state(struct drm_device *dev) }; int i; - if (INTEL_INFO(dev)->num_pipes == 0) + if (INTEL_INFO(dev_priv)->num_pipes == 0) return NULL; error = kzalloc(sizeof(*error), GFP_ATOMIC); @@ -16155,13 +16154,13 @@ intel_display_capture_error_state(struct drm_device *dev) error->plane[i].control = I915_READ(DSPCNTR(i)); error->plane[i].stride = I915_READ(DSPSTRIDE(i)); - if (INTEL_INFO(dev)->gen <= 3) { + if (INTEL_INFO(dev_priv)->gen <= 3) { error->plane[i].size = I915_READ(DSPSIZE(i)); error->plane[i].pos = I915_READ(DSPPOS(i)); } - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev)) error->plane[i].addr = I915_READ(DSPADDR(i)); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { error->plane[i].surface = I915_READ(DSPSURF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); } @@ -16173,7 +16172,7 @@ intel_display_capture_error_state(struct drm_device *dev) } /* Note: this does not include DSI transcoders. */ - error->num_transcoders = INTEL_INFO(dev)->num_pipes; + error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; if (HAS_DDI(dev_priv)) error->num_transcoders++; /* Account for eDP. */ @@ -16213,7 +16212,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, if (!error) return; - err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); + err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); if (IS_HASWELL(dev) || IS_BROADWELL(dev)) err_printf(m, "PWR_WELL_CTL2: %08x\n", error->power_well_driver); @@ -16227,13 +16226,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, err_printf(m, "Plane [%d]:\n", i); err_printf(m, " CNTR: %08x\n", error->plane[i].control); err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); - if (INTEL_INFO(dev)->gen <= 3) { + if (INTEL_INFO(dev_priv)->gen <= 3) { err_printf(m, " SIZE: %08x\n", error->plane[i].size); err_printf(m, " POS: %08x\n", error->plane[i].pos); } - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) + if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev)) err_printf(m, " ADDR: %08x\n", error->plane[i].addr); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { err_printf(m, " SURF: %08x\n", error->plane[i].surface); err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index da0c3d2..e2c565b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1471,7 +1471,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { int ret; ret = skl_update_scaler_crtc(pipe_config); if (ret) @@ -3157,7 +3157,7 @@ intel_dp_voltage_max(struct intel_dp *intel_dp) if (IS_BROXTON(dev)) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; - else if (INTEL_INFO(dev)->gen >= 9) { + else if (INTEL_INFO(dev_priv)->gen >= 9) { if (dev_priv->vbt.edp.low_vswing && port == PORT_A) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; @@ -3820,7 +3820,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); } - if (INTEL_INFO(dev)->gen >= 9 && + if (INTEL_INFO(dev_priv)->gen >= 9 && (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { uint8_t frame_sync_cap; @@ -5085,7 +5085,7 @@ bool intel_dp_is_edp(struct drm_device *dev, enum port port) * eDP not supported on g4x. so bail out early just * for a bit extra safety in case the VBT is bonkers. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_INFO(dev_priv)->gen < 5) return false; if (port == PORT_A) @@ -5399,7 +5399,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) return; } - if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { + if (INTEL_INFO(dev_priv)->gen >= 8 && !IS_CHERRYVIEW(dev)) { switch (index) { case DRRS_HIGH_RR: intel_dp_set_m_n(intel_crtc, M1_N1); @@ -5411,7 +5411,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) default: DRM_ERROR("Unsupported refreshrate type\n"); } - } else if (INTEL_INFO(dev)->gen > 6) { + } else if (INTEL_INFO(dev_priv)->gen > 6) { i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); u32 val; @@ -5688,7 +5688,7 @@ intel_dp_drrs_init(struct intel_connector *intel_connector, INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); mutex_init(&dev_priv->drrs.mutex); - if (INTEL_INFO(dev)->gen <= 6) { + if (INTEL_INFO(dev_priv)->gen <= 6) { DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); return NULL; } @@ -5840,7 +5840,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp->pps_pipe = INVALID_PIPE; /* intel_dp vfuncs */ - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -5849,7 +5849,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -6026,7 +6026,7 @@ intel_dp_init(struct drm_device *dev, } else { intel_encoder->pre_enable = g4x_pre_enable_dp; intel_encoder->enable = g4x_enable_dp; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_INFO(dev_priv)->gen >= 5) intel_encoder->post_disable = ilk_post_disable_dp; } diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 19efdd3..c7e970f 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -156,7 +156,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); /* PCH only available on ILK+ */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_INFO(dev_priv)->gen < 5) return; if (pll == NULL) diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index 79ac202..d4ccf35 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c @@ -698,7 +698,7 @@ int intel_fbdev_init(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0)) + if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0)) return -ENODEV; ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); @@ -711,7 +711,7 @@ int intel_fbdev_init(struct drm_device *dev) ifbdev->preferred_bpp = 32; ret = drm_fb_helper_init(dev, &ifbdev->helper, - INTEL_INFO(dev)->num_pipes, 4); + INTEL_INFO(dev_priv)->num_pipes, 4); if (ret) { kfree(ifbdev); return ret; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index a1db6a0..67b88de 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2142,7 +2142,7 @@ static int logical_render_ring_init(struct drm_device *dev) logical_ring_default_vfuncs(dev, engine); /* Override some for render ring. */ - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) engine->init_hw = gen9_init_render_ring; else engine->init_hw = gen8_init_render_ring; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 66e832b..6a5416a 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -123,7 +123,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_INFO(dev_priv)->gen < 4) { tmp = I915_READ(PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; @@ -186,7 +186,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder) /* Set the dithering flag on LVDS as needed, note that there is no * special lvds dither control bit on pch-split platforms, dithering is * only controlled through the PIPECONF reg. */ - if (INTEL_INFO(dev)->gen == 4) { + if (INTEL_INFO(dev_priv)->gen == 4) { /* Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. */ if (crtc->config->dither && crtc->config->pipe_bpp == 18) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 6694e92..a8c5269 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -905,7 +905,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) /* XXX: This is not the same logic as in the xorg driver, but more in * line with the intel documentation for the i965 */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { /* on i965 use the PGM reg to read out the autoscaler values */ ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; } else { @@ -1069,7 +1069,7 @@ static int intel_panel_fitter_pipe(struct drm_device *dev) u32 pfit_control; /* i830 doesn't have a panel fitter */ - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) + if (INTEL_INFO(dev_priv)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) return -1; pfit_control = I915_READ(PFIT_CONTROL); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 43b24a1..e8e778f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2126,14 +2126,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) wm[2] = (sskpd >> 12) & 0xFF; wm[3] = (sskpd >> 20) & 0x1FF; wm[4] = (sskpd >> 32) & 0x1FF; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { uint32_t sskpd = I915_READ(MCH_SSKPD); wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; - } else if (INTEL_INFO(dev)->gen >= 5) { + } else if (INTEL_INFO(dev_priv)->gen >= 5) { uint32_t mltr = I915_READ(MLTR_ILK); /* ILK primary LP0 latency is 700 ns */ @@ -2338,7 +2338,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) usable_level = max_level; /* ILK/SNB: LP2+ watermarks only w/o sprites */ - if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled) + if (INTEL_INFO(dev_priv)->gen <= 6 && pipe_wm->sprites_enabled) usable_level = 1; /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -2481,12 +2481,12 @@ static void ilk_wm_merge(struct drm_device *dev, int last_enabled_level = max_level; /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ - if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && + if ((INTEL_INFO(dev_priv)->gen <= 6 || IS_IVYBRIDGE(dev)) && config->num_pipes_active > 1) return; /* ILK: FBC WM must be disabled always */ - merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; + merged->fbc_wm_enabled = INTEL_INFO(dev_priv)->gen >= 6; /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { @@ -2792,7 +2792,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, previous->wm_lp_spr[0] != results->wm_lp_spr[0]) I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_INFO(dev_priv)->gen >= 7) { if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) @@ -3733,7 +3733,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); /* 5/6 split only in single pipe config on IVB+ */ - if (INTEL_INFO(dev)->gen >= 7 && + if (INTEL_INFO(dev_priv)->gen >= 7 && config.num_pipes_active == 1 && config.sprites_enabled) { ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); @@ -4102,7 +4102,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) hw->wm_lp[2] = I915_READ(WM3_LP_ILK); hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_INFO(dev_priv)->gen >= 7) { hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); } @@ -5140,7 +5140,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev) * No floor required for ring frequency on SKL. */ ring_freq = gpu_freq; - } else if (INTEL_INFO(dev)->gen >= 8) { + } else if (INTEL_INFO(dev_priv)->gen >= 8) { /* max(2 * GT, DDR). NB: GT is 50MHz units */ ring_freq = max(min_ring_freq, gpu_freq); } else if (IS_HASWELL(dev)) { @@ -5184,12 +5184,11 @@ void gen6_update_ring_freq(struct drm_device *dev) static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; u32 val, rp0; val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); - switch (INTEL_INFO(dev)->eu_total) { + switch (INTEL_INFO(dev_priv)->eu_total) { case 8: /* (2 * 4) config */ rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); @@ -5791,10 +5790,9 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; unsigned long val; - if (INTEL_INFO(dev)->gen != 5) + if (INTEL_INFO(dev_priv)->gen != 5) return 0; spin_lock_irq(&mchdev_lock); @@ -5834,11 +5832,10 @@ static int _pxvid_to_vd(u8 pxvid) static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) { - struct drm_device *dev = dev_priv->dev; const int vd = _pxvid_to_vd(pxvid); const int vm = vd - 1125; - if (INTEL_INFO(dev)->is_mobile) + if (INTEL_INFO(dev_priv)->is_mobile) return vm > 0 ? vm : 0; return vd; @@ -5879,9 +5876,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) void i915_update_gfx_val(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; - - if (INTEL_INFO(dev)->gen != 5) + if (INTEL_INFO(dev_priv)->gen != 5) return; spin_lock_irq(&mchdev_lock); @@ -5930,10 +5925,9 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; unsigned long val; - if (INTEL_INFO(dev)->gen != 5) + if (INTEL_INFO(dev_priv)->gen != 5) return 0; spin_lock_irq(&mchdev_lock); @@ -6246,7 +6240,7 @@ void intel_suspend_gt_powersave(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return; gen6_suspend_rps(dev); @@ -6261,11 +6255,11 @@ void intel_disable_gt_powersave(struct drm_device *dev) if (IS_IRONLAKE_M(dev)) { ironlake_disable_drps(dev); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { intel_suspend_gt_powersave(dev); mutex_lock(&dev_priv->rps.hw_lock); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) gen9_disable_rps(dev); else if (IS_CHERRYVIEW(dev)) cherryview_disable_rps(dev); @@ -6294,7 +6288,7 @@ static void intel_gen6_powersave_work(struct work_struct *work) cherryview_enable_rps(dev); } else if (IS_VALLEYVIEW(dev)) { valleyview_enable_rps(dev); - } else if (INTEL_INFO(dev)->gen >= 9) { + } else if (INTEL_INFO(dev_priv)->gen >= 9) { gen9_enable_rc6(dev); gen9_enable_rps(dev); if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) @@ -6335,7 +6329,7 @@ void intel_enable_gt_powersave(struct drm_device *dev) mutex_lock(&dev->struct_mutex); intel_init_emon(dev); mutex_unlock(&dev->struct_mutex); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { /* * PCU communication is slow and this doesn't need to be * done at any specific time, so do this out of our fast path @@ -6358,7 +6352,7 @@ void intel_reset_gt_powersave(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_INFO(dev_priv)->gen < 6) return; gen6_suspend_rps(dev); @@ -7199,7 +7193,7 @@ void intel_init_pm(struct drm_device *dev) i915_ironlake_get_mem_freq(dev); /* For FIFO watermark updates */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { skl_setup_wm_latency(dev); dev_priv->display.update_wm = skl_update_wm; } else if (HAS_PCH_SPLIT(dev)) { @@ -7249,7 +7243,7 @@ void intel_init_pm(struct drm_device *dev) dev_priv->display.update_wm = i9xx_update_wm; dev_priv->display.get_fifo_size = i9xx_get_fifo_size; } else if (IS_GEN2(dev)) { - if (INTEL_INFO(dev)->num_pipes == 1) { + if (INTEL_INFO(dev_priv)->num_pipes == 1) { dev_priv->display.update_wm = i845_update_wm; dev_priv->display.get_fifo_size = i845_get_fifo_size; } else { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index c3abae4..3205b03 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -204,7 +204,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_INFO(dev_priv)->gen >= 9) { uint32_t val; val = I915_READ(aux_ctl_reg); @@ -433,7 +433,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) /* Enable PSR on the panel */ hsw_psr_enable_sink(intel_dp); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_INFO(dev_priv)->gen >= 9) intel_psr_activate(intel_dp); } else { vlv_psr_setup_vsc(intel_dp); @@ -459,7 +459,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) * - On HSW/BDW we get a recoverable frozen screen until next * exit-activate sequence. */ - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_INFO(dev_priv)->gen < 9) schedule_delayed_work(&dev_priv->psr.work, msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2e864b7..36fedea 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -509,7 +509,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) * arises: do we still need this and if so how should we go about * invalidating the TLB? */ - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) { i915_reg_t reg = RING_INSTPM(engine->mmio_base); /* ring should be idle before issuing a sync flush*/ @@ -1215,7 +1215,7 @@ static int init_render_ring(struct intel_engine_cs *engine) return ret; /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) + if (INTEL_INFO(dev_priv)->gen >= 4 && INTEL_INFO(dev_priv)->gen < 7) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order @@ -1224,12 +1224,12 @@ static int init_render_ring(struct intel_engine_cs *engine) * * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv */ - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); /* Required for the hardware to program scanline values for waiting */ /* WaEnableFlushTlbInvalidationMode:snb */ - if (INTEL_INFO(dev)->gen == 6) + if (INTEL_INFO(dev_priv)->gen == 6) I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); @@ -1249,7 +1249,7 @@ static int init_render_ring(struct intel_engine_cs *engine) _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); } - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) + if (INTEL_INFO(dev_priv)->gen >= 6 && INTEL_INFO(dev_priv)->gen < 8) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); if (HAS_L3_DPF(dev)) @@ -1283,7 +1283,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req, enum intel_engine_id id; int ret, num_rings; - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; #undef MBOX_UPDATE_DWORDS @@ -1325,7 +1325,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req, enum intel_engine_id id; int ret, num_rings; - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; #undef MBOX_UPDATE_DWORDS @@ -1365,7 +1365,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req, int ret, num_rings; #define MBOX_UPDATE_DWORDS 3 - num_rings = hweight32(INTEL_INFO(dev)->ring_mask); + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); #undef MBOX_UPDATE_DWORDS @@ -2553,7 +2553,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno) struct drm_device *dev = engine->dev; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { + if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev)) @@ -2776,7 +2776,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->exec_id = I915_EXEC_RENDER; engine->mmio_base = RENDER_RING_BASE; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { if (i915_semaphore_is_enabled(dev)) { obj = i915_gem_alloc_object(dev, 4096); if (obj == NULL) { @@ -2808,11 +2808,11 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->semaphore.signal = gen8_rcs_signal; GEN8_RING_SEMAPHORE_INIT(engine); } - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_INFO(dev_priv)->gen >= 6) { engine->init_context = intel_rcs_ctx_init; engine->add_request = gen6_add_request; engine->flush = gen7_render_ring_flush; - if (INTEL_INFO(dev)->gen == 6) + if (INTEL_INFO(dev_priv)->gen == 6) engine->flush = gen6_render_ring_flush; engine->irq_get = gen6_ring_get_irq; engine->irq_put = gen6_ring_put_irq; @@ -2851,7 +2851,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; } else { engine->add_request = i9xx_add_request; - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_INFO(dev_priv)->gen < 4) engine->flush = gen2_render_ring_flush; else engine->flush = gen4_render_ring_flush; @@ -2872,9 +2872,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; else if (IS_GEN8(dev)) engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; - else if (INTEL_INFO(dev)->gen >= 6) + else if (INTEL_INFO(dev_priv)->gen >= 6) engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; - else if (INTEL_INFO(dev)->gen >= 4) + else if (INTEL_INFO(dev_priv)->gen >= 4) engine->dispatch_execbuffer = i965_dispatch_execbuffer; else if (IS_I830(dev) || IS_845G(dev)) engine->dispatch_execbuffer = i830_dispatch_execbuffer; @@ -2906,7 +2906,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) if (ret) return ret; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_INFO(dev_priv)->gen >= 5) { ret = intel_init_pipe_control(engine); if (ret) return ret; @@ -2925,7 +2925,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) engine->exec_id = I915_EXEC_BSD; engine->write_tail = ring_write_tail; - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_INFO(dev_priv)->gen >= 6) { engine->mmio_base = GEN6_BSD_RING_BASE; /* gen6 bsd needs a special wa for tail updates */ if (IS_GEN6(dev)) @@ -2934,7 +2934,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) engine->add_request = gen6_add_request; engine->get_seqno = gen6_ring_get_seqno; engine->set_seqno = ring_set_seqno; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; engine->irq_get = gen8_ring_get_irq; @@ -3038,7 +3038,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) engine->add_request = gen6_add_request; engine->get_seqno = gen6_ring_get_seqno; engine->set_seqno = ring_set_seqno; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; engine->irq_get = gen8_ring_get_irq; @@ -3097,7 +3097,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) engine->get_seqno = gen6_ring_get_seqno; engine->set_seqno = ring_set_seqno; - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_INFO(dev_priv)->gen >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; engine->irq_get = gen8_ring_get_irq; diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 2128fae..f12f879 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1271,13 +1271,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) return; /* Set the SDVO control regs. */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_INFO(dev_priv)->gen < 5) sdvox |= SDVO_BORDER_ENABLE; } else { sdvox = I915_READ(intel_sdvo->sdvo_reg); @@ -1296,7 +1296,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) if (intel_sdvo->has_hdmi_audio) sdvox |= SDVO_AUDIO_ENABLE; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_INFO(dev_priv)->gen >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { /* done in crtc_mode_set as it lives inside the dpll register */ @@ -1306,7 +1306,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - INTEL_INFO(dev)->gen < 5) + INTEL_INFO(dev_priv)->gen < 5) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 223129d..ead13ac 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1099,7 +1099,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder) set_color_conversion(dev_priv, color_conversion); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_INFO(dev_priv)->gen >= 4) I915_WRITE(TV_CLR_KNOBS, 0x00404000); else I915_WRITE(TV_CLR_KNOBS, 0x00606000); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index ac2ac07..0ccefa9 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -315,7 +315,7 @@ static void intel_uncore_ellc_detect(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; if ((IS_HASWELL(dev) || IS_BROADWELL(dev) || - INTEL_INFO(dev)->gen >= 9) && + INTEL_INFO(dev_priv)->gen >= 9) && (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) { /* The docs do not explain exactly how the calculation can be * made. It is somewhat guessable, but for now, it's always @@ -1259,7 +1259,7 @@ void intel_uncore_init(struct drm_device *dev) dev_priv->uncore.unclaimed_mmio_check = 1; - switch (INTEL_INFO(dev)->gen) { + switch (INTEL_INFO(dev_priv)->gen) { default: case 9: ASSIGN_WRITE_MMIO_VFUNCS(gen9); @@ -1343,7 +1343,7 @@ int i915_reg_read_ioctl(struct drm_device *dev, for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) && - (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) + (1 << INTEL_INFO(dev_priv)->gen & entry->gen_bitmask)) break; }
Where we have a suitable dev_priv pointer, we can use that rather than 'dev' for accessing INTEL_INFO(). This removes one level of memory reference, decreasing code size a little and possibly making everything a little faster. We could also do this for all the macros that implicitly use INTEL_INFO e.g. IS_CHERRYVIEW(). Coccinelle: @dev_priv_param@ function FUNC; idexpression struct drm_device *DEV; identifier DEV_PRIV; @@ FUNC(..., struct drm_i915_private *DEV_PRIV, ...) { <... INTEL_INFO ( - DEV + DEV_PRIV ) ...> } @dev_priv_local@ idexpression struct drm_device *DEV; identifier DEV_PRIV; expression E; @@ { ... ( struct drm_i915_private *DEV_PRIV; | struct drm_i915_private *DEV_PRIV = E; ) <... INTEL_INFO ( - DEV + DEV_PRIV ) ...> } followed by manually deleting 6 now-unused "dev" locals. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 66 +++++++------- drivers/gpu/drm/i915/i915_dma.c | 30 +++--- drivers/gpu/drm/i915/i915_drv.c | 4 +- drivers/gpu/drm/i915/i915_gem.c | 6 +- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +- drivers/gpu/drm/i915/i915_gem_fence.c | 8 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +-- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 32 +++---- drivers/gpu/drm/i915/i915_irq.c | 36 ++++---- drivers/gpu/drm/i915/i915_suspend.c | 20 ++-- drivers/gpu/drm/i915/intel_color.c | 16 ++-- drivers/gpu/drm/i915/intel_crt.c | 6 +- drivers/gpu/drm/i915/intel_ddi.c | 4 +- drivers/gpu/drm/i915/intel_display.c | 141 ++++++++++++++--------------- drivers/gpu/drm/i915/intel_dp.c | 20 ++-- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/intel_fbdev.c | 4 +- drivers/gpu/drm/i915/intel_lrc.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_overlay.c | 4 +- drivers/gpu/drm/i915/intel_pm.c | 50 +++++----- drivers/gpu/drm/i915/intel_psr.c | 6 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++++---- drivers/gpu/drm/i915/intel_sdvo.c | 8 +- drivers/gpu/drm/i915/intel_tv.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 6 +- 28 files changed, 270 insertions(+), 277 deletions(-)