@@ -2617,6 +2617,10 @@ struct drm_i915_cmd_table {
#define VEBOX_RING (1<<VECS)
#define BSD2_RING (1<<VCS2)
#define ALL_ENGINES (~0)
+#define I915_ENGINE_RESET_MASK ((1 << I915_EXEC_RENDER) | \
+ (1 << I915_EXEC_BSD) | \
+ (1 << I915_EXEC_BLT) | \
+ (1 << I915_EXEC_VEBOX))
#define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
#define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
@@ -45,7 +45,7 @@ struct i915_params i915 __read_mostly = {
.fastboot = 0,
.prefault_disable = 0,
.load_detect_test = 0,
- .reset = 1,
+ .reset = I915_ENGINE_RESET_MASK,
.invert_brightness = 0,
.disable_display = 0,
.enable_cmd_parser = 1,
@@ -109,7 +109,7 @@ MODULE_PARM_DESC(vbt_sdvo_panel_type,
"(-2=ignore, -1=auto [default], index in VBT BIOS table)");
module_param_named_unsafe(reset, i915.reset, int, 0600);
-MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset [default], 2=engine reset)");
+MODULE_PARM_DESC(reset, "Attempt GPU resets (0=disabled, 1=full gpu reset, 2=engine reset [default])");
module_param_named_unsafe(enable_hangcheck, i915.enable_hangcheck, bool, 0644);
MODULE_PARM_DESC(enable_hangcheck,