From patchwork Tue Apr 12 16:59:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 8812841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 99B589F3D1 for ; Tue, 12 Apr 2016 16:59:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CDCA12034F for ; Tue, 12 Apr 2016 16:59:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 04FDD2034C for ; Tue, 12 Apr 2016 16:59:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 123066E73C; Tue, 12 Apr 2016 16:59:53 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 97F3C6E73C for ; Tue, 12 Apr 2016 16:59:49 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP; 12 Apr 2016 09:59:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,475,1455004800"; d="scan'208";a="783401123" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by orsmga003.jf.intel.com with ESMTP; 12 Apr 2016 09:59:48 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 12 Apr 2016 17:59:29 +0100 Message-Id: <1460480381-8777-3-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1460480381-8777-1-git-send-email-arun.siluvery@linux.intel.com> References: <1460480381-8777-1-git-send-email-arun.siluvery@linux.intel.com> Subject: [Intel-gfx] [PATCH 02/14] drm/i915/tdr: Extend the idea of reset_counter to engine reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This change extends the idea of reset_counter variable to engine reset by creating additional variables for each engine. Least significant bit is set to mark the engine reset is pending and once reset is successful it is incremented again, this is further used to count the no of engine resets. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5424016..ca9b1ec 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1370,6 +1370,12 @@ struct i915_gpu_error { #define I915_RESET_IN_PROGRESS_FLAG 1 #define I915_WEDGED (1 << 31) + /* indicates request to reset engine */ +#define I915_ENGINE_RESET_IN_PROGRESS (1<<0) + + /* extending the idea of reset_counter to engine reset */ + atomic_t engine_reset_counter[I915_NUM_ENGINES]; + /** * Waitqueue to signal when the reset has completed. Used by clients * that wait for dev_priv->mm.wedged to settle. @@ -3059,6 +3065,19 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error) return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; } +static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error, + u32 engine_id) +{ + return unlikely(atomic_read(&error->engine_reset_counter[engine_id]) + & I915_ENGINE_RESET_IN_PROGRESS); +} + +static inline u32 i915_engine_reset_count(struct i915_gpu_error *error, + struct intel_engine_cs *engine) +{ + return (atomic_read(&error->engine_reset_counter[engine->id]) + 1) / 2; +} + static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) { return dev_priv->gpu_error.stop_rings == 0 ||