From patchwork Thu Apr 21 08:40:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shubhangi Shrivastava X-Patchwork-Id: 8897131 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F0D6ABF29F for ; Thu, 21 Apr 2016 08:38:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 111AC202EB for ; Thu, 21 Apr 2016 08:38:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 24919201FA for ; Thu, 21 Apr 2016 08:38:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C40E6EC1C; Thu, 21 Apr 2016 08:38:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 92E586EC18 for ; Thu, 21 Apr 2016 08:37:18 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 21 Apr 2016 01:37:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,512,1455004800"; d="scan'208";a="963355825" Received: from shubhangi-desktop.iind.intel.com ([10.223.25.115]) by fmsmga002.fm.intel.com with ESMTP; 21 Apr 2016 01:37:17 -0700 From: Shubhangi Shrivastava To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Apr 2016 14:10:28 +0530 Message-Id: <1461228031-2515-2-git-send-email-shubhangi.shrivastava@intel.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1461228031-2515-1-git-send-email-shubhangi.shrivastava@intel.com> References: <1461228031-2515-1-git-send-email-shubhangi.shrivastava@intel.com> Cc: Shubhangi Shrivastava Subject: [Intel-gfx] [PATCH 2/5] drm/i915: Read test values for lane_count and link_rate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP During automated test request for link training we are supposed to read the TEST_LANE_COUNT and TEST_LINK_RATE dpcd registers and use respective values in the next link training. This patch adds reading and updating of these values. Signed-off-by: Sivakumar Thulasimani Signed-off-by: Shubhangi Shrivastava --- drivers/gpu/drm/i915/intel_dp.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2a14603..0402a4b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4045,9 +4045,34 @@ intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) return true; } +/* + * This function reads TEST_LANE_COUNT & TEST_LINK_RATE and updates + * them to cached dpcd values, thus the new values are implicitly + * used by rest of the code without need to be aware of the change. + */ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) { uint8_t test_result = DP_TEST_ACK; + uint8_t dpcd_val, ret; + + ret = intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_TEST_LANE_COUNT, + &dpcd_val, 1); + + /* update values only if read returned 1 byte */ + if (ret == 1) { + dpcd_val &= DP_MAX_LANE_COUNT_MASK; + intel_dp->dpcd[DP_MAX_LANE_COUNT] &= ~(DP_MAX_LANE_COUNT_MASK); + intel_dp->dpcd[DP_MAX_LANE_COUNT] |= dpcd_val; + } + + ret = intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_TEST_LINK_RATE, + &dpcd_val, 1); + + if (ret == 1) + intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_val; + return test_result; }