From patchwork Fri Apr 29 18:21:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Bragg X-Patchwork-Id: 8984581 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CCD199F1D3 for ; Fri, 29 Apr 2016 18:22:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AAFD6201CE for ; Fri, 29 Apr 2016 18:22:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id BB347201ED for ; Fri, 29 Apr 2016 18:22:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7FE4D6E3FB; Fri, 29 Apr 2016 18:22:03 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id E964A6E3FB; Fri, 29 Apr 2016 18:22:00 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id r12so6819880wme.0; Fri, 29 Apr 2016 11:22:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=j/G/zyvv75LSdp1xyKGMKczzCVOQfsXT2V2vIJO2XJM=; b=nODwHrGBVJUfDjjZT8Gt4UW+i0KhGqfZPvEAC1Rbh+2U2jlD+NWzTp+86LJFAjJ6ru XqlJUVp1MFGdoOFHZ5z56nmlNjDpYVGZ78c+lUsBtSh4eiGtkeJAyo9bK9FWHXWt+Qbm SSevfWhJF8KrCUbgQ0ilQlDYmsxQKCYHbYnrqCVdr6ThpR5lcHM5lHM+QaFzAKjOl1H5 i7N5xIYkAbKSH8D450ERGfETXASChaAJgTYvY+LVJ0K27lS11YsJRPNSA5dUPWBTxIlS 7W7LYg6tkRSl/A17s6a2KhzEkGpW2EgSkmoigaa5WcE0BPj2Vl0x8At0ySn2lkWMoHlP befg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=j/G/zyvv75LSdp1xyKGMKczzCVOQfsXT2V2vIJO2XJM=; b=Z6oN0Ef+kjqbGrCDvJlU3nbnacur0eC7vg2xJHhi7L+LqCYUbyr0iTTZST8zdUpapO f8apXoklbNG+znBIS0osf5GljrOQoQSYIU2mJDTJl8Sc71IR8rX1YbBf1Q3op/7g10VE nnjoOiyTaFIOcRE6YhjIEZ15kpMk+EhGC0g+AQwkWiYoa8AX4zD0cGkxvl1KeHvsimLq 3tmKDG1RbXGeFNKQt2H64KRN7w7uhEvsKFcYQ01JqN7ctuOhVEPlBPR+HpsHtIeYDw0T ZLPEYJPeAHaVdbvj2VWzn4akzenH5SpZWIsbrfbILtihOR2v7hJd7kCj2iwv5v8Bf1pB 1K+w== X-Gm-Message-State: AOPr4FXp2a8ODg0juQrHAkk8rP3248Fct4uoQ1svKEeqLZNBjxL8C8MO8ewYX3joWyPuaQ== X-Received: by 10.194.32.165 with SMTP id k5mr10296628wji.23.1461954118758; Fri, 29 Apr 2016 11:21:58 -0700 (PDT) Received: from sixbynine.org (cpc26-heme10-2-0-cust305.9-1.cable.virginm.net. [86.3.57.50]) by smtp.gmail.com with ESMTPSA id vu4sm15961122wjc.27.2016.04.29.11.21.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 29 Apr 2016 11:21:58 -0700 (PDT) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Apr 2016 19:21:39 +0100 Message-Id: <1461954105-5940-5-git-send-email-robert@sixbynine.org> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1461954105-5940-1-git-send-email-robert@sixbynine.org> References: <1461954105-5940-1-git-send-email-robert@sixbynine.org> Cc: David Airlie , dri-devel@lists.freedesktop.org, Sourab Gupta , Deepak S , Daniel Vetter Subject: [Intel-gfx] [PATCH v2 04/10] drm/i915: don't whitelist oacontrol in cmd parser X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Being able to program OACONTROL from a non-privileged batch buffer is not sufficient to be able to configure the OA unit. This was originally allowed to help enable Mesa to expose OA counters via the INTEL_performance_query extension, but the current implementation based on programming OACONTROL via a batch buffer isn't able to report useable data without a more complete OA unit configuration. Mesa handles the possibility that writes to OACONTROL may not be allowed and so only advertises the extension after explicitly testing that a write to OACONTROL succeeds. Based on this; removing OACONTROL from the whitelist should be ok for userspace. Removing this simplifies adding a new kernel api for configuring the OA unit without needing to consider the possibility that userspace might trample on OACONTROL state which we'd like to start managing within the kernel instead. In particular running any Mesa based GL application currently results in clearing OACONTROL when initializing which would disable the capturing of metrics. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_cmd_parser.c | 33 ++------------------------------- 1 file changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 5724d80..ff2b57b 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -445,7 +445,6 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { REG64(PS_INVOCATION_COUNT), REG64(PS_DEPTH_COUNT), REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), - REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */ REG64(MI_PREDICATE_SRC0), REG64(MI_PREDICATE_SRC1), REG32(GEN7_3DPRIM_END_OFFSET), @@ -1044,8 +1043,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine) static bool check_cmd(const struct intel_engine_cs *engine, const struct drm_i915_cmd_descriptor *desc, const u32 *cmd, u32 length, - const bool is_master, - bool *oacontrol_set) + const bool is_master) { if (desc->flags & CMD_DESC_REJECT) { DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); @@ -1083,26 +1081,6 @@ static bool check_cmd(const struct intel_engine_cs *engine, } /* - * OACONTROL requires some special handling for - * writes. We want to make sure that any batch which - * enables OA also disables it before the end of the - * batch. The goal is to prevent one process from - * snooping on the perf data from another process. To do - * that, we need to check the value that will be written - * to the register. Hence, limit OACONTROL writes to - * only MI_LOAD_REGISTER_IMM commands. - */ - if (reg_addr == i915_mmio_reg_offset(GEN7_OACONTROL)) { - if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { - DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); - return false; - } - - if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) - *oacontrol_set = (cmd[offset + 1] != 0); - } - - /* * Check the value written to the register against the * allowed mask/value pair given in the whitelist entry. */ @@ -1186,7 +1164,6 @@ int i915_parse_cmds(struct intel_engine_cs *engine, { u32 *cmd, *batch_base, *batch_end; struct drm_i915_cmd_descriptor default_desc = { 0 }; - bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ int ret = 0; batch_base = copy_batch(shadow_batch_obj, batch_obj, @@ -1243,8 +1220,7 @@ int i915_parse_cmds(struct intel_engine_cs *engine, break; } - if (!check_cmd(engine, desc, cmd, length, is_master, - &oacontrol_set)) { + if (!check_cmd(engine, desc, cmd, length, is_master)) { ret = -EACCES; break; } @@ -1252,11 +1228,6 @@ int i915_parse_cmds(struct intel_engine_cs *engine, cmd += length; } - if (oacontrol_set) { - DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); - ret = -EINVAL; - } - if (cmd >= batch_end) { DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); ret = -EINVAL;