| Message ID | 1462275998-4864-4-git-send-email-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, May 03, 2016 at 02:46:38PM +0300, Mika Kahola wrote: > Read TMDS clock rate from DPCD for HDMI to filter out > modes that might require higher TMDS clock rate than > supported. > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 3 +++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++--- > 3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 74a04ce..0fd078c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -4591,6 +4591,9 @@ static void intel_dp_get_dfp(struct intel_dp *intel_dp) > if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) { > intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000; > DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk); > + } else if (!(intel_dp->dfp.type & DP_DS_PORT_TYPE_WIRELESS)) { > + intel_dp->dfp.tmds_clk = DIV_ROUND_CLOSEST(dfp_info[1] * 25 * 1000, 10); > + DRM_DEBUG_KMS("max TMDS clock is %d kHz\n", intel_dp->dfp.tmds_clk); > } > } > } > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 9798a59..8bf97da 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -799,6 +799,7 @@ struct intel_dp_dfp { > int type; > bool detailed_cap_info; > int dot_clk; /* pixel rate for VGA dongles */ > + int tmds_clk; > }; > > struct intel_dp { > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index e1012d6..70e8e17 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1170,13 +1170,14 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder) > static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) > { > struct drm_device *dev = intel_hdmi_to_dev(hdmi); > + int tmds_clock = hdmi_to_dig_port(hdmi)->dp.dfp.tmds_clk; > > if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) > - return 165000; > + return (tmds_clock > 0 ? min(165000, tmds_clock) : 165000); > else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) > - return 300000; > + return (tmds_clock > 0 ? min(300000, tmds_clock) : 300000); > else > - return 225000; > + return (tmds_clock > 0 ? min(225000, tmds_clock) : 225000); Changing limits for native HDMI ports isn't going to do much when dealing with active DP dongles. > } > > static enum drm_mode_status > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 74a04ce..0fd078c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -4591,6 +4591,9 @@ static void intel_dp_get_dfp(struct intel_dp *intel_dp) if (intel_dp->dfp.type & DP_DS_PORT_TYPE_VGA) { intel_dp->dfp.dot_clk = dfp_info[1] * 8 * 1000; DRM_DEBUG_KMS("max pixel rate for VGA is %d kHz\n", intel_dp->dfp.dot_clk); + } else if (!(intel_dp->dfp.type & DP_DS_PORT_TYPE_WIRELESS)) { + intel_dp->dfp.tmds_clk = DIV_ROUND_CLOSEST(dfp_info[1] * 25 * 1000, 10); + DRM_DEBUG_KMS("max TMDS clock is %d kHz\n", intel_dp->dfp.tmds_clk); } } } diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 9798a59..8bf97da 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -799,6 +799,7 @@ struct intel_dp_dfp { int type; bool detailed_cap_info; int dot_clk; /* pixel rate for VGA dongles */ + int tmds_clk; }; struct intel_dp { diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e1012d6..70e8e17 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1170,13 +1170,14 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder) static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) { struct drm_device *dev = intel_hdmi_to_dev(hdmi); + int tmds_clock = hdmi_to_dig_port(hdmi)->dp.dfp.tmds_clk; if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) - return 165000; + return (tmds_clock > 0 ? min(165000, tmds_clock) : 165000); else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) - return 300000; + return (tmds_clock > 0 ? min(300000, tmds_clock) : 300000); else - return 225000; + return (tmds_clock > 0 ? min(225000, tmds_clock) : 225000); } static enum drm_mode_status
Read TMDS clock rate from DPCD for HDMI to filter out modes that might require higher TMDS clock rate than supported. Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_hdmi.c | 7 ++++--- 3 files changed, 8 insertions(+), 3 deletions(-)