From patchwork Fri May 13 14:14:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9091801 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id EA55BBF29F for ; Fri, 13 May 2016 14:15:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7117B201F4 for ; Fri, 13 May 2016 14:15:13 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E51F9201BC for ; Fri, 13 May 2016 14:15:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0B5376E153; Fri, 13 May 2016 14:15:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id E28D76E153 for ; Fri, 13 May 2016 14:15:08 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 13 May 2016 07:15:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,614,1455004800"; d="scan'208";a="805594486" Received: from linux.intel.com ([10.23.219.25]) by orsmga003.jf.intel.com with ESMTP; 13 May 2016 07:15:09 -0700 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.45]) by linux.intel.com (Postfix) with ESMTP id AD8846A4006; Fri, 13 May 2016 08:02:40 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Fri, 13 May 2016 17:14:58 +0300 Message-Id: <1463148903-6337-2-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463148903-6337-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1463148903-6337-1-git-send-email-ander.conselvan.de.oliveira@intel.com> MIME-Version: 1.0 Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Rename struct dpll to struct intel_dpll X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Prefix struct dpll with intel_ to follow the convention in the driver. Cc: Ville Syrjälä Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 76 +++++++++++++++++------------------ drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 10 ++--- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 7 files changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7a0b513..5f9dda2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -577,7 +577,7 @@ struct intel_crtc_state; struct intel_initial_plane_config; struct intel_crtc; struct intel_limit; -struct dpll; +struct intel_dpll; struct drm_i915_display_funcs { int (*get_display_clock_speed)(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c454744..1387acd 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -948,7 +948,7 @@ static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, { struct intel_shared_dpll *pll; struct intel_dpll_hw_state *state; - struct dpll clock; + struct intel_dpll clock; /* For DDI ports we always use a shared PLL. */ if (WARN_ON(dpll == DPLL_ID_PRIVATE)) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 05c7533..048a5bf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -578,7 +578,7 @@ static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, * divided-down version of it. */ /* m1 is reserved as 0 in Pineview, n is a ring counter */ -static int pnv_calc_dpll_params(int refclk, struct dpll *clock) +static int pnv_calc_dpll_params(int refclk, struct intel_dpll *clock) { clock->m = clock->m2 + 2; clock->p = clock->p1 * clock->p2; @@ -590,12 +590,12 @@ static int pnv_calc_dpll_params(int refclk, struct dpll *clock) return clock->dot; } -static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) +static uint32_t i9xx_dpll_compute_m(struct intel_dpll *dpll) { return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); } -static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) +static int i9xx_calc_dpll_params(int refclk, struct intel_dpll *clock) { clock->m = i9xx_dpll_compute_m(clock); clock->p = clock->p1 * clock->p2; @@ -607,7 +607,7 @@ static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) return clock->dot; } -static int vlv_calc_dpll_params(int refclk, struct dpll *clock) +static int vlv_calc_dpll_params(int refclk, struct intel_dpll *clock) { clock->m = clock->m1 * clock->m2; clock->p = clock->p1 * clock->p2; @@ -619,7 +619,7 @@ static int vlv_calc_dpll_params(int refclk, struct dpll *clock) return clock->dot / 5; } -int chv_calc_dpll_params(int refclk, struct dpll *clock) +int chv_calc_dpll_params(int refclk, struct intel_dpll *clock) { clock->m = clock->m1 * clock->m2; clock->p = clock->p1 * clock->p2; @@ -640,7 +640,7 @@ int chv_calc_dpll_params(int refclk, struct dpll *clock) static bool intel_PLL_is_valid(struct drm_device *dev, const struct intel_limit *limit, - const struct dpll *clock) + const struct intel_dpll *clock) { if (clock->n < limit->n.min || limit->n.max < clock->n) INTELPllInvalid("n out of range\n"); @@ -712,11 +712,11 @@ i9xx_select_p2_div(const struct intel_limit *limit, static bool i9xx_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, - int target, int refclk, struct dpll *match_clock, - struct dpll *best_clock) + int target, int refclk, struct intel_dpll *match_clock, + struct intel_dpll *best_clock) { struct drm_device *dev = crtc_state->base.crtc->dev; - struct dpll clock; + struct intel_dpll clock; int err = target; memset(best_clock, 0, sizeof(*best_clock)); @@ -769,11 +769,11 @@ i9xx_find_best_dpll(const struct intel_limit *limit, static bool pnv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, - int target, int refclk, struct dpll *match_clock, - struct dpll *best_clock) + int target, int refclk, struct intel_dpll *match_clock, + struct intel_dpll *best_clock) { struct drm_device *dev = crtc_state->base.crtc->dev; - struct dpll clock; + struct intel_dpll clock; int err = target; memset(best_clock, 0, sizeof(*best_clock)); @@ -824,11 +824,11 @@ pnv_find_best_dpll(const struct intel_limit *limit, static bool g4x_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, - int target, int refclk, struct dpll *match_clock, - struct dpll *best_clock) + int target, int refclk, struct intel_dpll *match_clock, + struct intel_dpll *best_clock) { struct drm_device *dev = crtc_state->base.crtc->dev; - struct dpll clock; + struct intel_dpll clock; int max_n; bool found = false; /* approximately equals target * 0.00585 */ @@ -874,8 +874,8 @@ g4x_find_best_dpll(const struct intel_limit *limit, * best configuration and error found so far. Return the calculated error. */ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, - const struct dpll *calculated_clock, - const struct dpll *best_clock, + const struct intel_dpll *calculated_clock, + const struct intel_dpll *best_clock, unsigned int best_error_ppm, unsigned int *error_ppm) { @@ -917,12 +917,12 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, static bool vlv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, - int target, int refclk, struct dpll *match_clock, - struct dpll *best_clock) + int target, int refclk, struct intel_dpll *match_clock, + struct intel_dpll *best_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_device *dev = crtc->base.dev; - struct dpll clock; + struct intel_dpll clock; unsigned int bestppm = 1000000; /* min update 19.2 MHz */ int max_n = min(limit->n.max, refclk / 19200); @@ -976,13 +976,13 @@ vlv_find_best_dpll(const struct intel_limit *limit, static bool chv_find_best_dpll(const struct intel_limit *limit, struct intel_crtc_state *crtc_state, - int target, int refclk, struct dpll *match_clock, - struct dpll *best_clock) + int target, int refclk, struct intel_dpll *match_clock, + struct intel_dpll *best_clock) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_device *dev = crtc->base.dev; unsigned int best_error_ppm; - struct dpll clock; + struct intel_dpll clock; uint64_t m2; int found = false; @@ -1032,7 +1032,7 @@ chv_find_best_dpll(const struct intel_limit *limit, } bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, - struct dpll *best_clock) + struct intel_dpll *best_clock) { int refclk = 100000; const struct intel_limit *limit = &intel_limits_bxt; @@ -7041,19 +7041,19 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); } -static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) +static uint32_t pnv_dpll_compute_fp(struct intel_dpll *dpll) { return (1 << dpll->n) << 16 | dpll->m2; } -static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) +static uint32_t i9xx_dpll_compute_fp(struct intel_dpll *dpll) { return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; } static void i9xx_update_pll_dividers(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, - struct dpll *reduced_clock) + struct intel_dpll *reduced_clock) { struct drm_device *dev = crtc->base.dev; u32 fp, fp2 = 0; @@ -7430,7 +7430,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc, * be enabled. */ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, - const struct dpll *dpll) + const struct intel_dpll *dpll) { struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); @@ -7477,13 +7477,13 @@ void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) static void i9xx_compute_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, - struct dpll *reduced_clock) + struct intel_dpll *reduced_clock) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpll; bool is_sdvo; - struct dpll *clock = &crtc_state->dpll; + struct intel_dpll *clock = &crtc_state->dpll; i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); @@ -7553,12 +7553,12 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, static void i8xx_compute_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, - struct dpll *reduced_clock) + struct intel_dpll *reduced_clock) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; u32 dpll; - struct dpll *clock = &crtc_state->dpll; + struct intel_dpll *clock = &crtc_state->dpll; i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); @@ -8024,7 +8024,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; int pipe = pipe_config->cpu_transcoder; - struct dpll clock; + struct intel_dpll clock; u32 mdiv; int refclk = 100000; @@ -8121,7 +8121,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; int pipe = pipe_config->cpu_transcoder; enum dpio_channel port = vlv_pipe_to_channel(pipe); - struct dpll clock; + struct intel_dpll clock; u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; int refclk = 100000; @@ -8777,14 +8777,14 @@ int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) return DIV_ROUND_UP(bps, link_bw * 8); } -static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) +static bool ironlake_needs_fb_cb_tune(struct intel_dpll *dpll, int factor) { return i9xx_dpll_compute_m(dpll) < factor * dpll->n; } static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, - struct dpll *reduced_clock) + struct intel_dpll *reduced_clock) { struct drm_crtc *crtc = &intel_crtc->base; struct drm_device *dev = crtc->dev; @@ -8892,7 +8892,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; - struct dpll reduced_clock; + struct intel_dpll reduced_clock; bool has_reduced_clock = false; struct intel_shared_dpll *pll; const struct intel_limit *limit; @@ -10622,7 +10622,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, int pipe = pipe_config->cpu_transcoder; u32 dpll = pipe_config->dpll_hw_state.dpll; u32 fp; - struct dpll clock; + struct intel_dpll clock; int port_clock; int refclk = i9xx_pll_refclk(dev, pipe_config); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3633002..e85711a 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -49,7 +49,7 @@ struct dp_link_dpll { int clock; - struct dpll dpll; + struct intel_dpll dpll; }; static const struct dp_link_dpll gen4_dpll[] = { diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index c283ba4..3499ed2 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1508,7 +1508,7 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, int clock = crtc_state->port_clock; if (encoder->type == INTEL_OUTPUT_HDMI) { - struct dpll best_clock; + struct intel_dpll best_clock; /* Calculate HDMI div */ /* diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 8405ff7..2033ff1 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -266,7 +266,7 @@ struct intel_connector { struct intel_dp *mst_port; }; -struct dpll { +struct intel_dpll { /* given values */ int n; int m1, m2; @@ -484,7 +484,7 @@ struct intel_crtc_state { /* Settings for the intel dpll used on pretty much everything but * haswell. */ - struct dpll dpll; + struct intel_dpll dpll; /* Selected dpll when shared or NULL. */ struct intel_shared_dpll *shared_dpll; @@ -1206,7 +1206,7 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, enum pipe pipe); int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, - const struct dpll *dpll); + const struct intel_dpll *dpll); void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); int lpt_get_iclkip(struct drm_i915_private *dev_priv); @@ -1255,8 +1255,8 @@ void intel_dp_get_m_n(struct intel_crtc *crtc, void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n); int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, - struct dpll *best_clock); -int chv_calc_dpll_params(int refclk, struct dpll *pll_clock); + struct intel_dpll *best_clock); +int chv_calc_dpll_params(int refclk, struct intel_dpll *pll_clock); bool intel_crtc_active(struct drm_crtc *crtc); void hsw_enable_ips(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 2128fae..96bedd0 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1101,7 +1101,7 @@ intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) { unsigned dotclock = pipe_config->port_clock; - struct dpll *clock = &pipe_config->dpll; + struct intel_dpll *clock = &pipe_config->dpll; /* SDVO TV has fixed PLL values depend on its clock range, this mirrors vbios setting. */