From patchwork Fri May 13 14:15:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9091841 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E02059F457 for ; Fri, 13 May 2016 14:15:28 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E518820260 for ; Fri, 13 May 2016 14:15:27 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C759D20251 for ; Fri, 13 May 2016 14:15:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 21D0A6E33D; Fri, 13 May 2016 14:15:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DB756E33D for ; Fri, 13 May 2016 14:15:21 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP; 13 May 2016 07:15:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,614,1455004800"; d="scan'208";a="702279502" Received: from linux.intel.com ([10.23.219.25]) by FMSMGA003.fm.intel.com with ESMTP; 13 May 2016 07:15:14 -0700 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.45]) by linux.intel.com (Postfix) with ESMTP id 0CDC96A4006; Fri, 13 May 2016 08:02:44 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Fri, 13 May 2016 17:15:00 +0300 Message-Id: <1463148903-6337-4-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463148903-6337-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1463148903-6337-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Merge vlv/chv _prepare_pll() with their enable counterpart X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With the bulk of the dpio code moved out of the vlv/chv prepare pll functions into intel_dpio_phy.c, those functions became simple enough that they can be merged with the pll enabling function, that always succeeds the prepare call. Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_display.c | 82 ++++++++++++------------------------ 1 file changed, 26 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 06d9b96..3e494ec 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -104,10 +104,6 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, static void ironlake_set_pipeconf(struct drm_crtc *crtc); static void haswell_set_pipeconf(struct drm_crtc *crtc); static void haswell_set_pipemisc(struct drm_crtc *crtc); -static void vlv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); -static void chv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config); static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, @@ -1547,6 +1543,19 @@ static void vlv_enable_pll(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; + /* Enable Refclk */ + I915_WRITE(DPLL(pipe), + pipe_config->dpll_hw_state.dpll & + ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); + + /* No need to actually set up the DPLL with DSI */ + if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0) + vlv_phy_prepare_pll(crtc, pipe_config->dpll.n, + pipe_config->dpll.m1, pipe_config->dpll.m2, + pipe_config->dpll.p1, pipe_config->dpll.p2, + pipe_config->port_clock, + pipe_config->has_dp_encoder); + assert_pipe_disabled(dev_priv, pipe); /* PLL is protected by panel, make sure we can write it */ @@ -1596,6 +1605,17 @@ static void chv_enable_pll(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; + /* Enable Refclk and SSC */ + I915_WRITE(DPLL(pipe), + pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); + + /* No need to actually set up the DPLL with DSI */ + if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0) + chv_phy_prepare_pll(crtc, pipe_config->dpll.n, + pipe_config->dpll.m1, pipe_config->dpll.m2, + pipe_config->dpll.p1, pipe_config->dpll.p2, + pipe_config->dpll.vco); + assert_pipe_disabled(dev_priv, pipe); /* PLL is protected by panel, make sure we can write it */ @@ -6086,13 +6106,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) if (encoder->pre_pll_enable) encoder->pre_pll_enable(encoder); - if (IS_CHERRYVIEW(dev)) { - chv_prepare_pll(intel_crtc, intel_crtc->config); + if (IS_CHERRYVIEW(dev)) chv_enable_pll(intel_crtc, intel_crtc->config); - } else { - vlv_prepare_pll(intel_crtc, intel_crtc->config); + else vlv_enable_pll(intel_crtc, intel_crtc->config); - } for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_enable) @@ -7185,51 +7202,6 @@ static void chv_compute_dpll(struct intel_crtc *crtc, (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; } -static void vlv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - enum pipe pipe = crtc->pipe; - - /* Enable Refclk */ - I915_WRITE(DPLL(pipe), - pipe_config->dpll_hw_state.dpll & - ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); - - /* No need to actually set up the DPLL with DSI */ - if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) - return; - - vlv_phy_prepare_pll(crtc, pipe_config->dpll.n, - pipe_config->dpll.m1, pipe_config->dpll.m2, - pipe_config->dpll.p1, pipe_config->dpll.p2, - pipe_config->port_clock, - pipe_config->has_dp_encoder); - -} - -static void chv_prepare_pll(struct intel_crtc *crtc, - const struct intel_crtc_state *pipe_config) -{ - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = dev->dev_private; - enum pipe pipe = crtc->pipe; - - /* Enable Refclk and SSC */ - I915_WRITE(DPLL(pipe), - pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); - - /* No need to actually set up the DPLL with DSI */ - if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) - return; - - chv_phy_prepare_pll(crtc, pipe_config->dpll.n, - pipe_config->dpll.m1, pipe_config->dpll.m2, - pipe_config->dpll.p1, pipe_config->dpll.p2, - pipe_config->dpll.vco); -} - /** * vlv_force_pll_on - forcibly enable just the PLL * @dev_priv: i915 private structure @@ -7257,11 +7229,9 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, if (IS_CHERRYVIEW(dev)) { chv_compute_dpll(crtc, pipe_config); - chv_prepare_pll(crtc, pipe_config); chv_enable_pll(crtc, pipe_config); } else { vlv_compute_dpll(crtc, pipe_config); - vlv_prepare_pll(crtc, pipe_config); vlv_enable_pll(crtc, pipe_config); }