From patchwork Sun May 15 17:32:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9096671 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 540E6BF29F for ; Sun, 15 May 2016 17:38:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7DC0320122 for ; Sun, 15 May 2016 17:38:51 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 94DC92010E for ; Sun, 15 May 2016 17:38:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0F05A6E3A6; Sun, 15 May 2016 17:38:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id AC28C6E39F for ; Sun, 15 May 2016 17:38:24 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 15 May 2016 10:38:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,623,1455004800"; d="scan'208";a="977259756" Received: from dev-inno.bj.intel.com ([10.238.135.69]) by orsmga002.jf.intel.com with ESMTP; 15 May 2016 10:38:23 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, david.s.gordon@intel.com, joonas.lahtinen@linux.intel.com, kevin.tian@intel.com, zhiyuan.lv@intel.com Date: Mon, 16 May 2016 01:32:48 +0800 Message-Id: <1463333573-25112-11-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463333573-25112-1-git-send-email-zhi.a.wang@intel.com> References: <1463333573-25112-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH 10/15] drm/i915: Generate addressing mode bit from flag in context. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previously the addressing mode bit in context descriptor is generated from context PPGTT. As we allow context could be used without PPGTT, and we still need to know the addressing mode during context submission, a flag is introduced. And the addressing mode bit will be generated from this flag. Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 9 +++++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4ac88b2..7f050a3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -885,6 +885,7 @@ struct intel_context { bool skip_init_context; u32 ring_buffer_size; } engine[I915_NUM_ENGINES]; + bool use_48bit_addressing_mode; struct list_head link; }; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b952e37..b5b0849 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -343,6 +343,8 @@ i915_gem_create_context(struct drm_device *dev, ctx->ppgtt = ppgtt; } else ctx->ppgtt = dev_priv->mm.aliasing_ppgtt; + + ctx->use_48bit_addressing_mode = USES_FULL_48BIT_PPGTT(dev); } trace_i915_context_create(ctx); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 3f04784..0a96d4a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -214,7 +214,8 @@ enum { LEGACY_64B_CONTEXT }; #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 -#define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ +#define GEN8_CTX_ADDRESSING_MODE(ctx) \ + (ctx->use_48bit_addressing_mode ? \ LEGACY_64B_CONTEXT :\ LEGACY_32B_CONTEXT) enum { @@ -281,8 +282,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine) (engine->id == VCS || engine->id == VCS2); engine->ctx_desc_template = GEN8_CTX_VALID; - engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev_priv) << - GEN8_CTX_ADDRESSING_MODE_SHIFT; if (IS_GEN8(dev_priv)) engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; @@ -325,8 +324,10 @@ intel_lr_context_descriptor_update(struct intel_context *ctx, BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<ctx_desc_template; /* bits 0-11 */ + desc |= GEN8_CTX_ADDRESSING_MODE(ctx) << /* bits 3-4 */ + GEN8_CTX_ADDRESSING_MODE_SHIFT; desc |= ctx->engine[engine->id].lrc_vma->node.start + /* bits 12-31 */ - LRC_PPHWSP_PN * PAGE_SIZE; + LRC_PPHWSP_PN * PAGE_SIZE; desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ ctx->engine[engine->id].lrc_desc = desc;