From patchwork Tue May 17 08:19:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9110491 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 08FF99F1C1 for ; Tue, 17 May 2016 08:20:20 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 29D97201B4 for ; Tue, 17 May 2016 08:20:19 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3C38F20218 for ; Tue, 17 May 2016 08:20:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7112B6E651; Tue, 17 May 2016 08:20:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E69176E64A for ; Tue, 17 May 2016 08:19:31 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP; 17 May 2016 01:19:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="105209101" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.154]) by fmsmga004.fm.intel.com with ESMTP; 17 May 2016 01:19:30 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, joonas.lahtinen@linux.intel.com, chris@chris-wilson.co.uk, kevin.tian@intel.com, zhiyuan.lv@intel.com Date: Tue, 17 May 2016 04:19:07 -0400 Message-Id: <1463473149-5876-8-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> References: <1463473149-5876-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Introduce execlist context status change notification X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces an approach to track the execlist context status change. GVT-g uses GVT context as the "shadow context". The content inside GVT context will be copied back to guest after the context is idle. So GVT-g has to know the status of the execlist context. This function is configurable in the context creation service. Currently, Only GVT-g will create the "status-change-notification" enabled GEM context. v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/intel_lrc.c | 30 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.h | 7 +++++++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 91f69e5..9688006 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -882,9 +882,15 @@ struct intel_context { u64 lrc_desc; uint32_t *lrc_reg_state; bool initialised; +#if IS_ENABLED(CONFIG_DRM_I915_GVT) + struct atomic_notifier_head status_notifier_head; +#endif } engine[I915_NUM_ENGINES]; u32 ring_buffer_size; bool use_48bit_addressing_mode; +#if IS_ENABLED(CONFIG_DRM_I915_GVT) + bool enable_status_change_notification; +#endif struct list_head link; }; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d97623f..9069836 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -415,6 +415,20 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0, spin_unlock_irq(&dev_priv->uncore.lock); } +#if IS_ENABLED(CONFIG_DRM_I915_GVT) +static inline void execlists_context_status_change( + struct drm_i915_gem_request *req, + unsigned long status) +{ + if (!req->ctx->enable_status_change_notification) + return; + + atomic_notifier_call_chain( + &req->ctx->engine[req->engine->id].status_notifier_head, + status, req); +} +#endif + static void execlists_context_unqueue(struct intel_engine_cs *engine) { struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; @@ -450,6 +464,13 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine) if (unlikely(!req0)) return; +#if IS_ENABLED(CONFIG_DRM_I915_GVT) + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN); + + if (req1) + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN); +#endif + if (req0->elsp_submitted & engine->idle_lite_restore_wa) { /* * WaIdleLiteRestore: make sure we never cause a lite restore @@ -488,6 +509,10 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id) if (--head_req->elsp_submitted > 0) return 0; +#if IS_ENABLED(CONFIG_DRM_I915_GVT) + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT); +#endif + list_del(&head_req->execlist_link); i915_gem_request_unreference(head_req); @@ -2534,6 +2559,11 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx, ctx->engine[engine->id].state = ctx_obj; ctx->engine[engine->id].initialised = engine->init_context == NULL; +#if IS_ENABLED(CONFIG_DRM_I915_GVT) + if (ctx->enable_status_change_notification) + ATOMIC_INIT_NOTIFIER_HEAD( + &ctx->engine[engine->id].status_notifier_head); +#endif return 0; error_ringbuf: diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 1afba03..99f84c9 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -57,6 +57,13 @@ #define GEN8_CSB_READ_PTR(csb_status) \ (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) +#if IS_ENABLED(CONFIG_DRM_I915_GVT) +enum { + CONTEXT_SCHEDULE_IN = 0, + CONTEXT_SCHEDULE_OUT, +}; +#endif + /* Logical Rings */ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);