From patchwork Tue May 17 08:32:20 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9110601 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 344DEBF29F for ; Tue, 17 May 2016 08:32:56 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1BE3720328 for ; Tue, 17 May 2016 08:32:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3104920303 for ; Tue, 17 May 2016 08:32:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3AC56E65D; Tue, 17 May 2016 08:32:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id BDAA16E65D for ; Tue, 17 May 2016 08:32:33 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP; 17 May 2016 01:32:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="956150483" Received: from linux.intel.com ([10.23.219.25]) by orsmga001.jf.intel.com with ESMTP; 17 May 2016 01:32:33 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.237.66.167]) by linux.intel.com (Postfix) with ESMTP id C19966A4006; Tue, 17 May 2016 02:20:04 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 17 May 2016 11:32:20 +0300 Message-Id: <1463473942-5683-4-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH v2 3/5] drm/i915: Move VLV divider readout to intel_dpio_phy.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reading the dividers depends on sideband messaging, so it fits well if the other functions in intel_dpio_phy.c. The new function will also be used in a future patch. v2: Add _pll_ to the function name. (Ville) Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 11 +---------- drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 032f052..0c32ef3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3657,6 +3657,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder); void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, int port_clock, bool dp); +void vlv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, + enum pipe pipe, struct dpll *clock); int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 56ae2e9..9d42caf 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7796,22 +7796,13 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; int pipe = pipe_config->cpu_transcoder; struct dpll clock; - u32 mdiv; int refclk = 100000; /* In case of DSI, DPLL will not be used */ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) return; - mutex_lock(&dev_priv->sb_lock); - mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); - mutex_unlock(&dev_priv->sb_lock); - - clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; - clock.m2 = mdiv & DPIO_M2DIV_MASK; - clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; - clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; - clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; + vlv_phy_read_pll_dividers(dev_priv, pipe, &clock); pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); } diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index fcadc92..1856e5f 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -670,3 +670,19 @@ void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); mutex_unlock(&dev_priv->sb_lock); } + +void vlv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, + enum pipe pipe, struct dpll *clock) +{ + u32 mdiv; + + mutex_lock(&dev_priv->sb_lock); + mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); + mutex_unlock(&dev_priv->sb_lock); + + clock->m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; + clock->m2 = mdiv & DPIO_M2DIV_MASK; + clock->n = (mdiv >> DPIO_N_SHIFT) & 0xf; + clock->p1 = (mdiv >> DPIO_P1_SHIFT) & 7; + clock->p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; +}