From patchwork Tue May 17 08:32:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9110591 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 96267BF29F for ; Tue, 17 May 2016 08:32:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9ABE320306 for ; Tue, 17 May 2016 08:32:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 68FF2202DD for ; Tue, 17 May 2016 08:32:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 755526E65C; Tue, 17 May 2016 08:32:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 145C76E65D for ; Tue, 17 May 2016 08:32:36 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP; 17 May 2016 01:32:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="105215813" Received: from linux.intel.com ([10.23.219.25]) by fmsmga004.fm.intel.com with ESMTP; 17 May 2016 01:32:35 -0700 Received: from localhost (aconselv-mobl3.ger.corp.intel.com [10.237.66.167]) by linux.intel.com (Postfix) with ESMTP id 0BDEA6A4006; Tue, 17 May 2016 02:20:06 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 17 May 2016 11:32:21 +0300 Message-Id: <1463473942-5683-5-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> References: <1463473942-5683-1-git-send-email-ander.conselvan.de.oliveira@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH v2 4/5] drm/i915: Move CHV divider readout to intel_dpio_phy.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Reading the dividers depends on sideband messaging, so it fits well if the other functions in intel_dpio_phy.c. The new function will also be used in a future patch. v2: Add _pll_ to the new function name. (Ville) Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 18 +----------------- drivers/gpu/drm/i915/intel_dpio_phy.c | 24 ++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0c32ef3..894830b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3647,6 +3647,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder); void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2, int vco); +void chv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, + enum pipe pipe, struct dpll *clock); void vlv_set_phy_signal_level(struct intel_encoder *encoder, u32 demph_reg_value, u32 preemph_reg_value, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9d42caf..47cc150 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7882,30 +7882,14 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; int pipe = pipe_config->cpu_transcoder; - enum dpio_channel port = vlv_pipe_to_channel(pipe); struct dpll clock; - u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; int refclk = 100000; /* In case of DSI, DPLL will not be used */ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) return; - mutex_lock(&dev_priv->sb_lock); - cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); - pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); - pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); - pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); - pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); - mutex_unlock(&dev_priv->sb_lock); - - clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; - clock.m2 = (pll_dw0 & 0xff) << 22; - if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) - clock.m2 |= pll_dw2 & 0x3fffff; - clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; - clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; - clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; + chv_phy_read_pll_dividers(dev_priv, pipe, &clock); pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); } diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c index 1856e5f..bdd82df 100644 --- a/drivers/gpu/drm/i915/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c @@ -461,6 +461,30 @@ void chv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn, mutex_unlock(&dev_priv->sb_lock); } +void chv_phy_read_pll_dividers(struct drm_i915_private *dev_priv, + enum pipe pipe, struct dpll *clock) +{ + enum dpio_channel port = vlv_pipe_to_channel(pipe); + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; + + mutex_lock(&dev_priv->sb_lock); + cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); + pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); + pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); + pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); + pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); + mutex_unlock(&dev_priv->sb_lock); + + clock->m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; + clock->m2 = (pll_dw0 & 0xff) << 22; + if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) + clock->m2 |= pll_dw2 & 0x3fffff; + clock->n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; + clock->p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; + clock->p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; +} + + void vlv_set_phy_signal_level(struct intel_encoder *encoder, u32 demph_reg_value, u32 preemph_reg_value, u32 uniqtranscale_reg_value, u32 tx3_demph)