From patchwork Tue May 17 13:18:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9112351 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2F98D9F37F for ; Tue, 17 May 2016 13:18:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 804EC20303 for ; Tue, 17 May 2016 13:18:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 971D72010F for ; Tue, 17 May 2016 13:18:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5643C6E1B7; Tue, 17 May 2016 13:18:11 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 0AE0D6E1B7 for ; Tue, 17 May 2016 13:18:09 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 17 May 2016 06:18:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,324,1459839600"; d="scan'208";a="982863627" Received: from linux.intel.com ([10.23.219.25]) by fmsmga002.fm.intel.com with ESMTP; 17 May 2016 06:18:09 -0700 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.167]) by linux.intel.com (Postfix) with ESMTP id E22786A4006; Tue, 17 May 2016 07:05:40 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Tue, 17 May 2016 16:18:16 +0300 Message-Id: <1463491096-16453-1-git-send-email-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.5.5 Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH] drm/i915: Update kerneldoc for intel_dpll_mgr.c X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 68 ++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index c283ba4..36566f8 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -23,6 +23,13 @@ #include "intel_drv.h" +/** intel_get_shared_dpll_by_id - get a DPLL given its id + * @dev_priv: i915 device instance + * @id: pll id + * + * Returns: + * A pointer the DPLL with @id + */ struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, enum intel_dpll_id id) @@ -30,6 +37,13 @@ intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, return &dev_priv->shared_dplls[id]; } +/** intel_get_shared_dpll_id - get the id of a DPLL + * @dev_priv: i915 device instance + * @pll: the DPLL + * + * Returns: + * The id of @pll + */ enum intel_dpll_id intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) @@ -41,6 +55,15 @@ intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); } +/** intel_shared_dpll_config_get - get a reference to a DPLL for a crtc + * @config: a intel_shared_dpll_config struct + * @pll: pll to get a reference to + * @crtc: crtc that references the pll + * + * This gets a reference to @pll for @crtc. Internally is sets the pll's + * crtc_mask. @config should be the pll configuration in an atomic state. + * A crtc can reference a pll only once. + */ void intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, struct intel_shared_dpll *pll, @@ -52,6 +75,14 @@ intel_shared_dpll_config_get(struct intel_shared_dpll_config *config, config[id].crtc_mask |= 1 << crtc->pipe; } +/** intel_shared_dpll_config_put - release a reference to a DPLL for a crtc + * @config: a intel_shared_dpll_config struct + * @pll: pll that is referenced by @crtc + * @crtc: crtc that references the pll + * + * This releases the reference to @pll for @crtc. Internally is sets the pll's + * crtc_mask. @config should be the pll configuration in an atomic state. + */ void intel_shared_dpll_config_put(struct intel_shared_dpll_config *config, struct intel_shared_dpll *pll, @@ -80,6 +111,9 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, pll->name, onoff(state), onoff(cur_state)); } +/** intel_prepare_shared_dpll - call a dpll's mode_set hook + * @crtc: crtc which has a shared dpll + */ void intel_prepare_shared_dpll(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -102,12 +136,10 @@ void intel_prepare_shared_dpll(struct intel_crtc *crtc) } /** - * intel_enable_shared_dpll - enable PCH PLL - * @dev_priv: i915 private structure - * @pipe: pipe PLL to enable + * intel_enable_shared_dpll - enable a crtc's shared DPLL + * @crtc: crtc which has a shared DPLL * - * The PCH PLL needs to be enabled before the PCH transcoder, since it - * drives the transcoder clock. + * Enable the shared DPLL used by @crtc. */ void intel_enable_shared_dpll(struct intel_crtc *crtc) { @@ -148,6 +180,12 @@ out: mutex_unlock(&dev_priv->dpll_lock); } +/** + * intel_disable_shared_dpll - disable a crtc's shared DPLL + * @crtc: crtc which has a shared DPLL + * + * Disable the shared DPLL used by @crtc. + */ void intel_disable_shared_dpll(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -250,6 +288,11 @@ intel_reference_shared_dpll(struct intel_shared_dpll *pll, intel_shared_dpll_config_get(shared_dpll, pll, crtc); } +/** intel_shared_dpll_commit - make atomic state DPLL configuration effective + * @state: atomic state + * + * Makes the DPLL configuration in @state effective. + */ void intel_shared_dpll_commit(struct drm_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->dev); @@ -1725,6 +1768,11 @@ static const struct intel_dpll_mgr bxt_pll_mgr = { .get_dpll = bxt_get_dpll, }; +/** intel_shared_dpll_init - Initialize shared DPLLs + * @dev: drm device + * + * Initialize shared DPLLs for @dev. + */ void intel_shared_dpll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1768,6 +1816,16 @@ void intel_shared_dpll_init(struct drm_device *dev) intel_ddi_pll_init(dev); } +/** intel_get_shared_dpll - get a shared DPLL for crtc and encoder combination + * @crtc: crtc + * @crtc_state: atomic state for @crtc + * @encoder: encoder + * + * Find an appropriate DPLL for the given crtc and encoder combination. + * + * Returns: + * A shared DPLL to be used by @crtc and @encoder with the given @crtc_state. + */ struct intel_shared_dpll * intel_get_shared_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,