From patchwork Thu Jun 2 05:18:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: sourab.gupta@intel.com X-Patchwork-Id: 9149055 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 07B6460467 for ; Thu, 2 Jun 2016 05:17:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF32125EF7 for ; Thu, 2 Jun 2016 05:17:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E368E271FD; Thu, 2 Jun 2016 05:17:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 88E2025EF7 for ; Thu, 2 Jun 2016 05:17:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 851A06E381; Thu, 2 Jun 2016 05:17:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 873C96EAFD for ; Thu, 2 Jun 2016 05:17:27 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 01 Jun 2016 22:17:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,404,1459839600"; d="scan'208";a="967198492" Received: from sourab-desktop.iind.intel.com ([10.223.82.156]) by orsmga001.jf.intel.com with ESMTP; 01 Jun 2016 22:17:24 -0700 From: sourab.gupta@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 2 Jun 2016 10:48:44 +0530 Message-Id: <1464844729-2774-11-git-send-email-sourab.gupta@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464844729-2774-1-git-send-email-sourab.gupta@intel.com> References: <1464844729-2774-1-git-send-email-sourab.gupta@intel.com> Cc: Daniel Vetter , Sourab Gupta , Deepak S Subject: [Intel-gfx] [PATCH 10/15] drm/i915: Extract raw GPU timestamps from OA reports to forward in perf samples X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Sourab Gupta The OA reports contain the least significant 32 bits of the gpu timestamp. This patch enables retrieval of the timestamp field from OA reports, to forward as 64 bit raw gpu timestamps in the perf samples. Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_perf.c | 46 ++++++++++++++++++++++++++++++---------- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2a31b79..a9a123b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2196,6 +2196,7 @@ struct drm_i915_private { u32 ctx_flexeu0_off; u32 n_pending_periodic_samples; u32 pending_periodic_ts; + u64 last_gpu_ts; struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 4a6fc5e..65b4af6 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -781,6 +781,24 @@ static int append_sample(struct i915_perf_stream *stream, return 0; } +static u64 get_gpu_ts_from_oa_report(struct drm_i915_private *dev_priv, + const u8 *report) +{ + u32 sample_ts = *(u32 *)(report + 4); + u32 delta; + + /* + * NB: We have to assume we're updating last_gpu_ts frequently + * enough that it's never possible to see multiple overflows before + * we compare sample_ts to last_gpu_ts. Since this is significantly + * large duration (~6min for 80ns ts base), we can safely assume so. + */ + delta = sample_ts - (u32)dev_priv->perf.oa.last_gpu_ts; + dev_priv->perf.oa.last_gpu_ts += delta; + + return dev_priv->perf.oa.last_gpu_ts; +} + static int append_oa_buffer_sample(struct i915_perf_stream *stream, struct i915_perf_read_state *read_state, const u8 *report) @@ -817,10 +835,9 @@ static int append_oa_buffer_sample(struct i915_perf_stream *stream, if (sample_flags & SAMPLE_TAG) data.tag = dev_priv->perf.last_tag; - /* Derive timestamp from OA report, after scaling with the ts base */ -#warning "FIXME: append_oa_buffer_sample: derive the timestamp from OA report" + /* Derive timestamp from OA report */ if (sample_flags & SAMPLE_TS) - data.ts = 0; + data.ts = get_gpu_ts_from_oa_report(dev_priv, report); if (sample_flags & SAMPLE_OA_REPORT) data.report = report; @@ -1272,6 +1289,7 @@ static int append_one_cs_sample(struct i915_perf_stream *stream, enum intel_engine_id id = stream->engine; struct sample_data data = { 0 }; u32 sample_flags = stream->sample_flags; + u64 gpu_ts = 0; int ret = 0; if (sample_flags & SAMPLE_OA_REPORT) { @@ -1288,6 +1306,9 @@ static int append_one_cs_sample(struct i915_perf_stream *stream, U32_MAX); if (ret) return ret; + + if (sample_flags & SAMPLE_TS) + gpu_ts = get_gpu_ts_from_oa_report(dev_priv, report); } if (sample_flags & SAMPLE_OA_SOURCE_INFO) @@ -1309,17 +1330,14 @@ static int append_one_cs_sample(struct i915_perf_stream *stream, } if (sample_flags & SAMPLE_TS) { - /* For RCS, if OA samples are also being collected, derive the - * timestamp from OA report, after scaling with the TS base. + /* If OA sampling is enabled, derive the ts from OA report. * Else, forward the timestamp collected via command stream. */ -#warning "FIXME: append_one_cs_sample: derive the timestamp from OA report" - if (sample_flags & SAMPLE_OA_REPORT) - data.ts = 0; - else - data.ts = *(u64 *) + if (!(sample_flags & SAMPLE_OA_REPORT)) + gpu_ts = *(u64 *) (dev_priv->perf.command_stream_buf[id].addr + node->ts_offset); + data.ts = gpu_ts; } return append_sample(stream, read_state, &data); @@ -2055,9 +2073,15 @@ static void i915_ring_stream_enable(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; - if (stream->sample_flags & SAMPLE_OA_REPORT) + if (stream->sample_flags & SAMPLE_OA_REPORT) { dev_priv->perf.oa.ops.oa_enable(dev_priv); + if (stream->sample_flags & SAMPLE_TS) + dev_priv->perf.oa.last_gpu_ts = + I915_READ64_2x32(GT_TIMESTAMP_COUNT, + GT_TIMESTAMP_COUNT_UDW); + } + if (stream->cs_mode || dev_priv->perf.oa.periodic) hrtimer_start(&dev_priv->perf.poll_check_timer, ns_to_ktime(POLL_PERIOD), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 92f9eaa..be7e008 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -591,6 +591,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define PS_DEPTH_COUNT _MMIO(0x2350) #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) +/* Timestamp count register */ +#define GT_TIMESTAMP_COUNT _MMIO(0x2358) +#define GT_TIMESTAMP_COUNT_UDW _MMIO(0x2358 + 4) + /* There are the 4 64-bit counter registers, one for each stream output */ #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4)