From patchwork Thu Jun 2 16:36:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9150901 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 78F6060221 for ; Thu, 2 Jun 2016 16:39:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 69A9428319 for ; Thu, 2 Jun 2016 16:39:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E89028326; Thu, 2 Jun 2016 16:39:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 08AEA28319 for ; Thu, 2 Jun 2016 16:39:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B4836EACE; Thu, 2 Jun 2016 16:39:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 0E6116EB3F for ; Thu, 2 Jun 2016 16:39:24 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 02 Jun 2016 09:39:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,407,1459839600"; d="scan'208";a="820370346" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.146]) by orsmga003.jf.intel.com with ESMTP; 02 Jun 2016 09:39:21 -0700 From: Zhi Wang To: intel-gfx@lists.freedesktop.org, tvrtko.ursulin@linux.intel.com, joonas.lahtinen@linux.intel.com, kevin.tian@intel.com, zhiyuan.lv@intel.com, chris@chris-wilson.co.uk Date: Thu, 2 Jun 2016 12:36:18 -0400 Message-Id: <1464885380-7056-8-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464885380-7056-1-git-send-email-zhi.a.wang@intel.com> References: <1464885380-7056-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH v6 7/9] drm/i915: Introduce execlist context status change notification X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch introduces an approach to track the execlist context status change. GVT-g uses GVT context as the "shadow context". The content inside GVT context will be copied back to guest after the context is idle. So GVT-g has to know the status of the execlist context. This function is configurable in the context creation service. Currently, Only GVT-g will create the "status-change-notification" enabled GEM context. v6: - When !CONFIG_DRM_I915_GVT, make GVT code as dead code then compiler could automatically eliminate them for us. (Chris) - Always initialize the notifier header, so it could be switched on/off at runtime. (Chris) v5: - Only compile this feature when CONFIG_DRM_I915_GVT is enabled.(Tvrtko) Signed-off-by: Zhi Wang Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.h | 5 +++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f6cb60a..dee72d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -877,9 +877,11 @@ struct i915_gem_context { u64 lrc_desc; int pin_count; bool initialised; + struct atomic_notifier_head status_notifier; } engine[I915_NUM_ENGINES]; u32 lrc_ring_buffer_size; u32 lrc_addressing_mode_bits; + bool enable_lrc_status_change_notification; struct list_head link; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index ffb436c..96d20c8 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -404,6 +404,22 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0, spin_unlock_irq(&dev_priv->uncore.lock); } +static inline void execlists_context_status_change( + struct drm_i915_gem_request *rq, + unsigned long status) +{ + /* The compiler should be fine with the dead-code elimination */ + if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) + return; + + if (!rq->ctx->enable_lrc_status_change_notification) + return; + + atomic_notifier_call_chain( + &rq->ctx->engine[rq->engine->id].status_notifier, + status, rq); +} + static void execlists_context_unqueue(struct intel_engine_cs *engine) { struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; @@ -439,6 +455,11 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine) if (unlikely(!req0)) return; + execlists_context_status_change(req0, CONTEXT_SCHEDULE_IN); + + if (req1) + execlists_context_status_change(req1, CONTEXT_SCHEDULE_IN); + if (req0->elsp_submitted & engine->idle_lite_restore_wa) { /* * WaIdleLiteRestore: make sure we never cause a lite restore @@ -477,6 +498,8 @@ execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id) if (--head_req->elsp_submitted > 0) return 0; + execlists_context_status_change(head_req, CONTEXT_SCHEDULE_OUT); + list_del(&head_req->execlist_link); i915_gem_request_unreference(head_req); @@ -2489,6 +2512,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, ce->ringbuf = ringbuf; ce->state = ctx_obj; ce->initialised = engine->init_context == NULL; + ATOMIC_INIT_NOTIFIER_HEAD(&ce->status_notifier); return 0; diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index e133c33..7a7ae8d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -68,6 +68,11 @@ enum { #define GEN8_CSB_READ_PTR(csb_status) \ (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) +enum { + CONTEXT_SCHEDULE_IN = 0, + CONTEXT_SCHEDULE_OUT, +}; + /* Logical Rings */ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request); int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);