| Message ID | 1464954000-35400-1-git-send-email-arun.siluvery@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 03, 2016 at 12:40:00PM +0100, Arun Siluvery wrote: > Kernel only need to add a register to HW whitelist, required for a > preemption related issue. > > Reference: HSD#2131039 > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e307725..1f6040a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells { > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) > > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) > +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) > #define GEN8_CS_CHICKEN1 _MMIO(0x2580) > > /* GEN7 chicken */ > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 8d35a39..1f9d3a4 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > + if (ret) > + return ret; > + > /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ > ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); > if (ret) > -- > 1.9.1 > Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 06/06/2016 14:58, Patchwork wrote: > == Series Details == > > Series: drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear (rev2) > URL : https://patchwork.freedesktop.org/series/8218/ > State : warning > > == Summary == > > Series 8218v2 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear > http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/2/mbox > > Test gem_basic: > Subgroup create-close: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test gem_busy: > Subgroup basic-parallel-bsd: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test gem_close_race: > Subgroup basic-threads: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test gem_cs_tlb: > Subgroup basic-default: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test gem_ctx_param: > Subgroup basic: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test gem_exec_flush: > Subgroup basic-uc-set-default: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test gem_flink_basic: > Subgroup basic: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Test gem_mmap_gtt: > Subgroup basic-small-copy-xy: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup basic-write: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup basic-write-gtt: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Test kms_addfb_basic: > Subgroup addfb25-x-tiled-mismatch: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup bad-pitch-65536: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup bo-too-small: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup no-handle: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > Subgroup too-high: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup unused-modifier: > dmesg-warn -> PASS (ro-skl-i7-6700hq) > Subgroup unused-offsets: > pass -> DMESG-WARN (ro-skl-i7-6700hq) > All dmesg-warn are because of a single known issue, [BAT SKL] *ERROR* Potential atomic update failure on pipe A https://bugs.freedesktop.org/show_bug.cgi?id=95632 regards Arun > fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8 > fi-hsw-i7-4770k total:209 pass:190 dwarn:0 dfail:0 fail:0 skip:19 > fi-skl-i5-6260u total:209 pass:198 dwarn:0 dfail:0 fail:0 skip:11 > fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25 > fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39 > ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39 > ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37 > ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23 > ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19 > ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0 > ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57 > ro-ivb-i7-3770 total:102 pass:75 dwarn:0 dfail:0 fail:0 skip:26 > ro-ivb2-i7-3770 total:102 pass:79 dwarn:0 dfail:0 fail:0 skip:22 > ro-skl-i7-6700hq total:204 pass:172 dwarn:11 dfail:0 fail:0 skip:21 > ro-snb-i7-2620M total:102 pass:72 dwarn:0 dfail:0 fail:0 skip:29 > ro-bdw-i5-5250u failed to connect after reboot > ro-bdw-i7-5557U failed to connect after reboot > > Results at /archive/results/CI_IGT_test/RO_Patchwork_1118/ > > 1930b31 drm-intel-nightly: 2016y-06m-06d-06h-53m-02s UTC integration manifest > 29cf429 drm/i915/gen9: Add WaVFEStateAfterPipeControlwithMediaStateClear > >
On 06/06/16 11:03, Arun Siluvery wrote: > On 06/06/2016 14:58, Patchwork wrote: >> == Series Details == >> >> Series: drm/i915/gen9: Add >> WaVFEStateAfterPipeControlwithMediaStateClear (rev2) >> URL : https://patchwork.freedesktop.org/series/8218/ >> State : warning >> >> == Summary == >> >> Series 8218v2 drm/i915/gen9: Add >> WaVFEStateAfterPipeControlwithMediaStateClear >> http://patchwork.freedesktop.org/api/1.0/series/8218/revisions/2/mbox >> >> Test gem_basic: >> Subgroup create-close: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Test gem_busy: >> Subgroup basic-parallel-bsd: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Test gem_close_race: >> Subgroup basic-threads: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Test gem_cs_tlb: >> Subgroup basic-default: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Test gem_ctx_param: >> Subgroup basic: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Test gem_exec_flush: >> Subgroup basic-uc-set-default: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Test gem_flink_basic: >> Subgroup basic: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Test gem_mmap_gtt: >> Subgroup basic-small-copy-xy: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Subgroup basic-write: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Subgroup basic-write-gtt: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Test kms_addfb_basic: >> Subgroup addfb25-x-tiled-mismatch: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Subgroup bad-pitch-65536: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Subgroup bo-too-small: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Subgroup no-handle: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> Subgroup too-high: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Subgroup unused-modifier: >> dmesg-warn -> PASS (ro-skl-i7-6700hq) >> Subgroup unused-offsets: >> pass -> DMESG-WARN (ro-skl-i7-6700hq) >> > > All dmesg-warn are because of a single known issue, > > [BAT SKL] *ERROR* Potential atomic update failure on pipe A > https://bugs.freedesktop.org/show_bug.cgi?id=95632 Merged, thanks for the patch and review. Regards, Tvrtko
Quoting Arun Siluvery (2016-06-03 12:40:00) > Kernel only need to add a register to HW whitelist, required for a > preemption related issue. > > Reference: HSD#2131039 > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e307725..1f6040a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells { > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) > > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) > +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) > #define GEN8_CS_CHICKEN1 _MMIO(0x2580) > > /* GEN7 chicken */ > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 8d35a39..1f9d3a4 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > + if (ret) > + return ret; What is for exactly? This register is not context saved, so... -Chris
s/Arun/Jeff + Jon/ This W/A would seem to be breaking context isolation as it is not context saved. Thus it is a candidate for being removed. I have to say I did not get any wiser from reading the HSD, so can you guys bring some insight here? Regards, Joonas On Wed, 2017-11-01 at 22:44 +0000, Chris Wilson wrote: > Quoting Arun Siluvery (2016-06-03 12:40:00) > > Kernel only need to add a register to HW whitelist, required for a > > preemption related issue. > > > > Reference: HSD#2131039 > > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 1 + > > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index e307725..1f6040a 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells { > > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) > > > > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) > > +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) > > #define GEN8_CS_CHICKEN1 _MMIO(0x2580) > > > > /* GEN7 chicken */ > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 8d35a39..1f9d3a4 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) > > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > > GEN8_LQSC_FLUSH_COHERENT_LINES)); > > > > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ > > + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); > > + if (ret) > > + return ret; > > What is for exactly? This register is not context saved, so... > -Chris > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e307725..1f6040a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells { #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8) #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) #define GEN8_CS_CHICKEN1 _MMIO(0x2580) /* GEN7 chicken */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8d35a39..1f9d3a4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | GEN8_LQSC_FLUSH_COHERENT_LINES)); + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); + if (ret) + return ret; + /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret)
Kernel only need to add a register to HW whitelist, required for a preemption related issue. Reference: HSD#2131039 Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 2 files changed, 6 insertions(+)