From patchwork Tue Jun 7 15:18:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Zhi A" X-Patchwork-Id: 9161623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F298B60467 for ; Tue, 7 Jun 2016 15:20:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4AE71FF65 for ; Tue, 7 Jun 2016 15:20:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D9B0A21C9A; Tue, 7 Jun 2016 15:20:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 45D011FF65 for ; Tue, 7 Jun 2016 15:20:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7878C6E7D2; Tue, 7 Jun 2016 15:20:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 2291A6E7CA for ; Tue, 7 Jun 2016 15:20:29 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP; 07 Jun 2016 08:20:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,433,1459839600"; d="scan'208";a="823397306" Received: from zhiwang1-mobl4.ccr.corp.intel.com (HELO inno-VirtualBox.fi.intel.com) ([10.237.66.159]) by orsmga003.jf.intel.com with ESMTP; 07 Jun 2016 08:20:27 -0700 From: Zhi Wang To: chris@chris-wilson.co.uk, zhiyuan.lv@intel.com, kevin.tian@intel.com, tvrtko.ursulin@linux.intel.com, intel-gfx@lists.freedesktop.org Date: Tue, 7 Jun 2016 11:18:42 -0400 Message-Id: <1465312727-2211-7-git-send-email-zhi.a.wang@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465312727-2211-1-git-send-email-zhi.a.wang@intel.com> References: <1465312727-2211-1-git-send-email-zhi.a.wang@intel.com> Subject: [Intel-gfx] [PATCH v7 06/11] drm/i915: Introduce host graphics memory partition for GVT-g X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Bing Niu This patch introduces host graphics memory partition when GVT-g is enabled. Under GVT-g, i915 host driver only owned limited graphics resources, others are managed by GVT-g resource allocator and kept for other vGPUs. v7: - Add comments about low/high GM size for host. (Joonas) v6: - Remove kernel parameters used to configure GGTT owned by host. (Chris) - Other coding style comments from Chris. - Add more comments for reviewer. v3: - Remove fence partition, will use i915 fence stealing in future.(Kevin) - Santinize GVT host gm kernel parameters. (Joonas) v2: - Address all coding-style comments from Joonas previously. - Fix errors and warnning reported by checkpatch.pl. (Joonas) - Move the graphs into the header files. (Daniel) Signed-off-by: Bing Niu Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_vgpu.c | 23 +++++++++++++++++------ drivers/gpu/drm/i915/intel_gvt.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index d41a29e..f343335 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -189,14 +189,25 @@ int intel_vgt_balloon(struct drm_i915_private *dev_priv) unsigned long unmappable_base, unmappable_size, unmappable_end; int ret, i; - if (!intel_vgpu_active(dev_priv)) + if (intel_gvt_active(dev_priv)) { + /* Retrieve GGTT partition information from macros */ + mappable_base = 0; + mappable_size = INTEL_GVT_HOST_LOW_GM_SIZE; + unmappable_base = dev_priv->ggtt.mappable_end; + unmappable_size = INTEL_GVT_HOST_HIGH_GM_SIZE; + } else if (intel_vgpu_active(dev_priv)) { + /* Retrieve GGTT partition information from PVINFO */ + mappable_base = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.base)); + mappable_size = I915_READ( + vgtif_reg(avail_rs.mappable_gmadr.size)); + unmappable_base = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.base)); + unmappable_size = I915_READ( + vgtif_reg(avail_rs.nonmappable_gmadr.size)); + } else return 0; - mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); - mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); - unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); - unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); - mappable_end = mappable_base + mappable_size; unmappable_end = unmappable_base + unmappable_size; diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h index 91e129f..d0d71d1 100644 --- a/drivers/gpu/drm/i915/intel_gvt.h +++ b/drivers/gpu/drm/i915/intel_gvt.h @@ -26,6 +26,42 @@ #include "gvt/gvt.h" +/* + * Under GVT-g, i915 host driver only owned limited graphics resources, + * others are managed by GVT-g resource allocator and kept for other vGPUs. + * + * For graphics memory space partition, a typical layout looks like: + * + * +-------+-----------------------+------+-----------------------+ + * |* Host | *GVT-g Resource |* Host| *GVT-g Resource | + * | Owned | Allocator Managed | Owned| Allocator Managed | + * | | | | | + * +---------------+-------+----------------------+-------+-------+ + * | | | | | | | | | + * | i915 | vm 1 | vm 2 | vm 3 | i915 | vm 1 | vm 2 | vm 3 | + * | | | | | | | | | + * +-------+-------+-------+--------------+-------+-------+-------+ + * | Aperture | Hidden | + * +-------------------------------+------------------------------+ + * | GGTT memory space | + * +--------------------------------------------------------------+ + */ + +/* GGTT memory space owned by host */ +/* + * This amount is heavily related to the max screen resolution / multiple + * display in *host*. If you are using a 4K monitor or multiple display + * monitor, probably you should enlarge the low gm size. + */ +#define INTEL_GVT_HOST_LOW_GM_SIZE (96 * 1024 * 1024) + +/* + * This amount is related to the GPU workload in host. If you wish to run + * heavy workload like 3D gaming, media transcoding *in host* and encounter + * performance drops, probably you should enlarge the high gm size. + */ +#define INTEL_GVT_HOST_HIGH_GM_SIZE (384 * 1024 * 1024) + #ifdef CONFIG_DRM_I915_GVT extern int intel_gvt_init(struct drm_i915_private *dev_priv); extern void intel_gvt_cleanup(struct drm_i915_private *dev_priv);