| Message ID | 1465580157-31867-1-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/06/16 18:35, Dave Gordon wrote: > More Coccinellery ... > > Wherever we find "INTEL_INFO(dev)->gen", and have a suitable > "dev_priv" in scope, replace it with "INTEL_GEN(dev_priv)". > At this time, we've found 189 instances, and each replacement > saves one memory cycle at runtime and two bytes of codespace > (~360 bytes total text size reduction). > > @dev_priv_param@ > function FUNC; > idexpression struct drm_device *DEV; > identifier DEV_PRIV; > @@ > FUNC(..., struct drm_i915_private *DEV_PRIV, ...) > { > <... > - INTEL_INFO(DEV)->gen > + INTEL_GEN(DEV_PRIV) > ...> > } > > @dev_priv_local@ > idexpression struct drm_device *DEV; > identifier DEV_PRIV; > expression E; > @@ > { > ... > ( > struct drm_i915_private *DEV_PRIV; > | > struct drm_i915_private *DEV_PRIV = E; > ) > <... > - INTEL_INFO(DEV)->gen > + INTEL_GEN(DEV_PRIV) > ...> > } > > Plus manual deletion of one now-unused local "dev". > > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 52 +++++++------- > drivers/gpu/drm/i915/i915_dma.c | 16 ++--- > drivers/gpu/drm/i915/i915_drv.c | 2 +- > drivers/gpu/drm/i915/i915_gem.c | 4 +- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-- > drivers/gpu/drm/i915/i915_gem_fence.c | 8 +-- > drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- > drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 14 ++-- > drivers/gpu/drm/i915/i915_irq.c | 12 ++-- > drivers/gpu/drm/i915/i915_suspend.c | 20 +++--- > drivers/gpu/drm/i915/intel_color.c | 2 +- > drivers/gpu/drm/i915/intel_crt.c | 6 +- > drivers/gpu/drm/i915/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++--------------- > drivers/gpu/drm/i915/intel_dp.c | 20 +++--- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/intel_lvds.c | 4 +- > drivers/gpu/drm/i915/intel_pm.c | 18 ++--- > drivers/gpu/drm/i915/intel_psr.c | 4 +- > drivers/gpu/drm/i915/intel_sdvo.c | 8 +-- > drivers/gpu/drm/i915/intel_tv.c | 2 +- > 22 files changed, 167 insertions(+), 168 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index e4f2c55..6a106d5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -672,7 +672,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) > intel_crtc_get_vblank_counter(crtc)); > seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); > else > addr = I915_READ(DSPADDR(crtc->plane)); > @@ -869,7 +869,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(GEN8_PCU_IIR)); > seq_printf(m, "PCU interrupt enable:\t%08x\n", > I915_READ(GEN8_PCU_IER)); > - } else if (INTEL_INFO(dev)->gen >= 8) { > + } else if (INTEL_GEN(dev_priv) >= 8) { > seq_printf(m, "Master Interrupt Control:\t%08x\n", > I915_READ(GEN8_MASTER_IRQ)); > > @@ -995,7 +995,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(GTIMR)); > } > for_each_engine(engine, dev_priv) { > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_GEN(dev_priv) >= 6) { > seq_printf(m, > "Graphics Interrupt mask (%s): %08x\n", > engine->name, I915_READ_IMR(engine)); > @@ -1232,7 +1232,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > "efficient (RPe) frequency: %d MHz\n", > intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); > mutex_unlock(&dev_priv->rps.hw_lock); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_GEN(dev_priv) >= 6) { > u32 rp_state_limits; > u32 gt_perf_status; > u32 rp_state_cap; > @@ -1745,7 +1745,7 @@ static int i915_fbc_fc_get(void *data, u64 *val) > struct drm_device *dev = data; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) > + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev)) > return -ENODEV; > > *val = dev_priv->fbc.false_color; > @@ -1759,7 +1759,7 @@ static int i915_fbc_fc_set(void *data, u64 val) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 reg; > > - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) > + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev)) > return -ENODEV; > > mutex_lock(&dev_priv->fbc.lock); > @@ -1795,7 +1795,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) > seq_printf(m, "Enabled by kernel parameter: %s\n", > yesno(i915.enable_ips)); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > seq_puts(m, "Currently: unknown\n"); > } else { > if (I915_READ(IPS_CTL) & IPS_ENABLE) > @@ -2266,7 +2266,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > I915_READ16(C0DRB3)); > seq_printf(m, "C1DRB3 = 0x%04x\n", > I915_READ16(C1DRB3)); > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_GEN(dev_priv) >= 6) { > seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", > I915_READ(MAD_DIMM_C0)); > seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", > @@ -2275,7 +2275,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > I915_READ(MAD_DIMM_C2)); > seq_printf(m, "TILECTL = 0x%08x\n", > I915_READ(TILECTL)); > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_GEN(dev_priv) >= 8) > seq_printf(m, "GAMTARBMODE = 0x%08x\n", > I915_READ(GAMTARBMODE)); > else > @@ -2380,9 +2380,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) > return ret; > intel_runtime_pm_get(dev_priv); > > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_GEN(dev_priv) >= 8) > gen8_ppgtt_info(m, dev); > - else if (INTEL_INFO(dev)->gen >= 6) > + else if (INTEL_GEN(dev_priv) >= 6) > gen6_ppgtt_info(m, dev); > > mutex_lock(&dev->filelist_mutex); > @@ -2741,7 +2741,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data) > u64 power; > u32 units; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > @@ -3338,7 +3338,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) > enum pipe pipe; > int plane; > > - if (INTEL_INFO(dev)->gen < 9) > + if (INTEL_GEN(dev_priv) < 9) > return 0; > > drm_modeset_lock_all(dev); > @@ -4091,7 +4091,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, > > if (IS_GEN2(dev)) > ret = i8xx_pipe_crc_ctl_reg(&source, &val); > - else if (INTEL_INFO(dev)->gen < 5) > + else if (INTEL_GEN(dev_priv) < 5) > ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); > else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) > ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); > @@ -4578,7 +4578,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.pri_latency; > @@ -4594,7 +4594,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.spr_latency; > @@ -4610,7 +4610,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) > struct drm_i915_private *dev_priv = dev->dev_private; > const uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.cur_latency; > @@ -4701,7 +4701,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.pri_latency; > @@ -4717,7 +4717,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.spr_latency; > @@ -4733,7 +4733,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > uint16_t *latencies; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > latencies = dev_priv->wm.skl_latency; > else > latencies = to_i915(dev)->wm.cur_latency; > @@ -4973,7 +4973,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -4996,7 +4996,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > u32 hw_max, hw_min; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -5040,7 +5040,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > struct drm_i915_private *dev_priv = dev->dev_private; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -5063,7 +5063,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, > u32 hw_max, hw_min; > int ret; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return -ENODEV; > > flush_delayed_work(&dev_priv->rps.delayed_resume_work); > @@ -5341,7 +5341,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) > struct drm_device *dev = inode->i_private; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return 0; > > intel_runtime_pm_get(dev_priv); > @@ -5355,7 +5355,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) > struct drm_device *dev = inode->i_private; > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return 0; > > intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c > index 07edaed..afd4598 100644 > --- a/drivers/gpu/drm/i915/i915_dma.c > +++ b/drivers/gpu/drm/i915/i915_dma.c > @@ -165,7 +165,7 @@ static int i915_getparam(struct drm_device *dev, void *data, > value = 1; > break; > case I915_PARAM_HAS_EXEC_CONSTANTS: > - value = INTEL_INFO(dev)->gen >= 4; > + value = INTEL_GEN(dev_priv) >= 4; > break; > case I915_PARAM_HAS_RELAXED_DELTA: > value = 1; > @@ -261,12 +261,12 @@ static int i915_get_bridge_dev(struct drm_device *dev) > intel_alloc_mchbar_resource(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp_lo, temp_hi = 0; > u64 mchbar_addr; > int ret; > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); > pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); > mchbar_addr = ((u64)temp_hi << 32) | temp_lo; > @@ -293,7 +293,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) > return ret; > } > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > pci_write_config_dword(dev_priv->bridge_dev, reg + 4, > upper_32_bits(dev_priv->mch_res.start)); > > @@ -307,7 +307,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) > intel_setup_mchbar(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; > u32 temp; > bool enabled; > > @@ -347,7 +347,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) > intel_teardown_mchbar(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; > + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; > > if (dev_priv->mchbar_need_disable) { > if (IS_I915G(dev) || IS_I915GM(dev)) { > @@ -948,7 +948,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) > cherryview_sseu_info_init(dev); > else if (IS_BROADWELL(dev)) > broadwell_sseu_info_init(dev); > - else if (INTEL_INFO(dev)->gen >= 9) > + else if (INTEL_GEN(dev_priv) >= 9) > gen9_sseu_info_init(dev); > > info->has_snoop = !info->has_llc; > @@ -1143,7 +1143,7 @@ static int i915_mmio_setup(struct drm_device *dev) > * the register BAR remains the same size for all the earlier > * generations up to Ironlake. > */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_GEN(dev_priv) < 5) > mmio_size = 512 * 1024; > else > mmio_size = 2 * 1024 * 1024; > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 872c6060..97ddba5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -998,7 +998,7 @@ int i915_reset(struct drm_i915_private *dev_priv) > * previous concerns that it doesn't respond well to some forms > * of re-init after reset. > */ > - if (INTEL_INFO(dev)->gen > 5) > + if (INTEL_GEN(dev_priv) > 5) > intel_enable_gt_powersave(dev_priv); > > return 0; > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index eae8d7a..4aeee79 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4778,7 +4778,7 @@ void i915_gem_init_swizzling(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen < 5 || > + if (INTEL_GEN(dev_priv) < 5 || > dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) > return; > > @@ -4895,7 +4895,7 @@ int i915_gem_init_engines(struct drm_device *dev) > u32 temp = I915_READ(GEN7_MSG_CTL); > temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); > I915_WRITE(GEN7_MSG_CTL, temp); > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_GEN(dev_priv) >= 7) { > u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); > temp &= ~RESET_PCH_HANDSHAKE_ENABLE; > I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 8097698..86e052c 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -335,7 +335,7 @@ static inline uint64_t gen8_noncanonical_addr(uint64_t address) > offset & PAGE_MASK); > iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > offset += sizeof(uint32_t); > > if (offset_in_page(offset) == 0) { > @@ -1254,19 +1254,19 @@ static bool only_mappable_for_reloc(unsigned int flags) > } > > if (instp_mode != dev_priv->relative_constants_mode) { > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > DRM_DEBUG("no rel constants on pre-gen4\n"); > return -EINVAL; > } > > - if (INTEL_INFO(dev)->gen > 5 && > + if (INTEL_GEN(dev_priv) > 5 && > instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { > DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); > return -EINVAL; > } > > /* The HW changed the meaning on this bit on gen6 */ > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_GEN(dev_priv) >= 6) > instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; > } > break; > diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c > index 2b6bdc2..013e69c 100644 > --- a/drivers/gpu/drm/i915/i915_gem_fence.c > +++ b/drivers/gpu/drm/i915/i915_gem_fence.c > @@ -62,7 +62,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg, > i915_reg_t fence_reg_lo, fence_reg_hi; > int fence_pitch_shift; > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_GEN(dev_priv) >= 6) { > fence_reg_lo = FENCE_REG_GEN6_LO(reg); > fence_reg_hi = FENCE_REG_GEN6_HI(reg); > fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; > @@ -209,7 +209,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, > i830_write_fence_reg(dev, reg, obj); > else if (IS_GEN3(dev)) > i915_write_fence_reg(dev, reg, obj); > - else if (INTEL_INFO(dev)->gen >= 4) > + else if (INTEL_GEN(dev_priv) >= 4) > i965_write_fence_reg(dev, reg, obj); > > /* And similarly be paranoid that no direct access to this region > @@ -553,7 +553,7 @@ void i915_gem_restore_fences(struct drm_device *dev) > uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; > uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; > > - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { > + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev)) { While we are churning :), could looks for both dev_priv and dev in the same condition like here and tidy those. > /* > * On BDW+, swizzling is not used. We leave the CPU memory > * controller in charge of optimizing memory accesses without > @@ -563,7 +563,7 @@ void i915_gem_restore_fences(struct drm_device *dev) > */ > swizzle_x = I915_BIT_6_SWIZZLE_NONE; > swizzle_y = I915_BIT_6_SWIZZLE_NONE; > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_GEN(dev_priv) >= 6) { > if (dev_priv->preserve_bios_swizzle) { > if (I915_READ(DISP_ARB_CTL) & > DISP_TILE_SURFACE_SWIZZLING) { > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 4668477..ac860af 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2324,7 +2324,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) > /* Don't bother messing with faults pre GEN6 as we have little > * documentation supporting that it's a good idea. > */ > - if (INTEL_INFO(dev)->gen < 6) > + if (INTEL_GEN(dev_priv) < 6) > return; > > i915_check_and_clear_faults(dev_priv); > @@ -3054,7 +3054,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) > > pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); > ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); > } else if (IS_CHERRYVIEW(dev)) { > @@ -3173,10 +3173,10 @@ int i915_ggtt_init_hw(struct drm_device *dev) > struct i915_ggtt *ggtt = &dev_priv->ggtt; > int ret; > > - if (INTEL_INFO(dev)->gen <= 5) { > + if (INTEL_GEN(dev_priv) <= 5) { > ggtt->probe = i915_gmch_probe; > ggtt->base.cleanup = i915_gmch_remove; > - } else if (INTEL_INFO(dev)->gen < 8) { > + } else if (INTEL_GEN(dev_priv) < 8) { > ggtt->probe = gen6_gmch_probe; > ggtt->base.cleanup = gen6_gmch_remove; > > @@ -3186,7 +3186,7 @@ int i915_ggtt_init_hw(struct drm_device *dev) > ggtt->base.pte_encode = hsw_pte_encode; > else if (IS_VALLEYVIEW(dev)) > ggtt->base.pte_encode = byt_pte_encode; > - else if (INTEL_INFO(dev)->gen >= 7) > + else if (INTEL_GEN(dev_priv) >= 7) > ggtt->base.pte_encode = ivb_pte_encode; > else > ggtt->base.pte_encode = snb_pte_encode; > @@ -3271,7 +3271,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) > WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); > } > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) > chv_setup_private_ppat(dev_priv); > else > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index e9cd822..7b8383e 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -108,7 +108,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > * > */ > base = 0; > - if (INTEL_INFO(dev)->gen >= 3) { > + if (INTEL_GEN(dev_priv) >= 3) { > u32 bsm; > > pci_read_config_dword(dev->pdev, INTEL_BSM, &bsm); > @@ -192,7 +192,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) > return 0; > > /* make sure we don't clobber the GTT if it's within stolen memory */ > - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { > + if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { > struct { > u32 start, end; > } stolen[2] = { > @@ -405,7 +405,7 @@ int i915_gem_init_stolen(struct drm_device *dev) > mutex_init(&dev_priv->mm.stolen_lock); > > #ifdef CONFIG_INTEL_IOMMU > - if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { > + if (intel_iommu_gfx_mapped && INTEL_GEN(dev_priv) < 8) { > DRM_INFO("DMAR active, disabling use of stolen memory\n"); > return 0; > } > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 34ff245..1da09c5 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -382,7 +382,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > > err_printf(m, "EIR: 0x%08x\n", error->eir); > err_printf(m, "IER: 0x%08x\n", error->ier); > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > for (i = 0; i < 4; i++) > err_printf(m, "GTIER gt %d: 0x%08x\n", i, > error->gtier[i]); > @@ -401,10 +401,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > err_printf(m, " INSTDONE_%d: 0x%08x\n", i, > error->extra_instdone[i]); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_GEN(dev_priv) >= 6) { > err_printf(m, "ERROR: 0x%08x\n", error->error); > > - if (INTEL_INFO(dev)->gen >= 8) > + if (INTEL_GEN(dev_priv) >= 8) > err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", > error->fault_data1, error->fault_data0); > > @@ -1251,7 +1251,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > if (IS_GEN7(dev)) > error->err_int = I915_READ(GEN7_ERR_INT); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); > error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); > } > @@ -1263,10 +1263,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > } > > /* 2: Registers which belong to multiple generations */ > - if (INTEL_INFO(dev)->gen >= 7) > + if (INTEL_GEN(dev_priv) >= 7) > error->forcewake = I915_READ_FW(FORCEWAKE_MT); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_GEN(dev_priv) >= 6) { > error->derrmr = I915_READ(DERRMR); > error->error = I915_READ(ERROR_GEN6); > error->done_reg = I915_READ(DONE_REG); > @@ -1282,7 +1282,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, > if (HAS_HW_CONTEXTS(dev)) > error->ccid = I915_READ(CCID); > > - if (INTEL_INFO(dev)->gen >= 8) { > + if (INTEL_GEN(dev_priv) >= 8) { > error->ier = I915_READ(GEN8_DE_MISC_IER); > for (i = 0; i < 4; i++) > error->gtier[i] = I915_READ(GEN8_GT_IER(i)); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 4378a65..2b7d292 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2729,7 +2729,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) > unsigned long irqflags; > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > i915_enable_pipestat(dev_priv, pipe, > PIPE_START_VBLANK_INTERRUPT_STATUS); > else > @@ -2744,7 +2744,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > unsigned long irqflags; > - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > + uint32_t bit = (INTEL_GEN(dev_priv) >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > DE_PIPE_VBLANK(pipe); > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > @@ -2798,7 +2798,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) > { > struct drm_i915_private *dev_priv = dev->dev_private; > unsigned long irqflags; > - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > + uint32_t bit = (INTEL_GEN(dev_priv) >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : > DE_PIPE_VBLANK(pipe); > > spin_lock_irqsave(&dev_priv->irq_lock, irqflags); > @@ -3303,7 +3303,7 @@ static void gen5_gt_irq_reset(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > GEN5_IRQ_RESET(GT); > - if (INTEL_INFO(dev)->gen >= 6) > + if (INTEL_GEN(dev_priv) >= 6) > GEN5_IRQ_RESET(GEN6_PM); > } > > @@ -3640,7 +3640,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > > GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_GEN(dev_priv) >= 6) { > /* > * RPS interrupts will get enabled/disabled on demand when RPS > * itself is enabled/disabled. > @@ -3658,7 +3658,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > u32 display_mask, extra_mask; > > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_GEN(dev_priv) >= 7) { > display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | > DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | > DE_PLANEB_FLIP_DONE_IVB | > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index 34e061a..048a7e1 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -34,13 +34,13 @@ static void i915_save_display(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > /* Display arbitration control */ > - if (INTEL_INFO(dev)->gen <= 4) > + if (INTEL_GEN(dev_priv) <= 4) > dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); > > /* LVDS state */ > if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) > dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); > - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > + else if (INTEL_GEN(dev_priv) <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > dev_priv->regfile.saveLVDS = I915_READ(LVDS); > > /* Panel power sequencer */ > @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev) > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); > dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); > - } else if (INTEL_INFO(dev)->gen <= 4) { > + } else if (INTEL_GEN(dev_priv) <= 4) { > dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); > dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); > dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); > @@ -57,7 +57,7 @@ static void i915_save_display(struct drm_device *dev) > } > > /* save FBC interval */ > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) > + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev)) > dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); > } > > @@ -67,7 +67,7 @@ static void i915_restore_display(struct drm_device *dev) > u32 mask = 0xffffffff; > > /* Display arbitration */ > - if (INTEL_INFO(dev)->gen <= 4) > + if (INTEL_GEN(dev_priv) <= 4) > I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); > > mask = ~LVDS_PORT_EN; > @@ -75,7 +75,7 @@ static void i915_restore_display(struct drm_device *dev) > /* LVDS state */ > if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) > I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); > - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > + else if (INTEL_GEN(dev_priv) <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) > I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); > > /* Panel power sequencer */ > @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev) > I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); > I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); > I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); > - } else if (INTEL_INFO(dev)->gen <= 4) { > + } else if (INTEL_GEN(dev_priv) <= 4) { > I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); > I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); > I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); > @@ -95,7 +95,7 @@ static void i915_restore_display(struct drm_device *dev) > intel_fbc_global_disable(dev_priv); > > /* restore FBC interval */ > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) > + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev)) > I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); > > i915_redisable_vga(dev); > @@ -115,7 +115,7 @@ int i915_save_state(struct drm_device *dev) > &dev_priv->regfile.saveGCDGMBUS); > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_GEN(dev_priv) < 7) > dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); > > /* Memory Arbitration state */ > @@ -161,7 +161,7 @@ int i915_restore_state(struct drm_device *dev) > i915_restore_display(dev); > > /* Cache mode state */ > - if (INTEL_INFO(dev)->gen < 7) > + if (INTEL_GEN(dev_priv) < 7) > I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | > 0xffff0000); > > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 522f5a2..778dec1 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -179,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) > I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); > I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); > > - if (INTEL_INFO(dev)->gen > 6) { > + if (INTEL_GEN(dev_priv) > 6) { > uint16_t postoff = 0; > > if (intel_crtc->config->limited_color_range) > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index 6229681..668f57e 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -152,7 +152,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) > const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; > u32 adpa; > > - if (INTEL_INFO(dev)->gen >= 5) > + if (INTEL_GEN(dev_priv) >= 5) > adpa = ADPA_HOTPLUG_BITS; > else > adpa = 0; > @@ -653,7 +653,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) > if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { > if (intel_crt_detect_ddc(connector)) > status = connector_status_connected; > - else if (INTEL_INFO(dev)->gen < 4) > + else if (INTEL_GEN(dev_priv) < 4) > status = intel_crt_load_detect(crt, > to_intel_crtc(connector->state->crtc)->pipe); > else if (i915.load_detect_test) > @@ -719,7 +719,7 @@ static void intel_crt_reset(struct drm_connector *connector) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crt *crt = intel_attached_crt(connector); > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_GEN(dev_priv) >= 5) { > u32 adpa; > > adpa = I915_READ(crt->adpa_reg); > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 022b41d..71d8fb1 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1671,7 +1671,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) > if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) > I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | > DPLL_CTRL2_DDI_CLK_OFF(port))); > - else if (INTEL_INFO(dev)->gen < 9) > + else if (INTEL_GEN(dev_priv) < 9) > I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); > > if (type == INTEL_OUTPUT_HDMI) { > @@ -1705,7 +1705,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) > } else if (type == INTEL_OUTPUT_EDP) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > - if (port == PORT_A && INTEL_INFO(dev)->gen < 9) > + if (port == PORT_A && INTEL_GEN(dev_priv) < 9) > intel_dp_stop_link_train(intel_dp); > > intel_edp_backlight_on(intel_dp); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 473c8fd..984b9fc 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1120,7 +1120,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) > enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; > enum pipe pipe = crtc->pipe; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > i915_reg_t reg = PIPECONF(cpu_transcoder); > > /* Wait for the Pipe State to go off */ > @@ -1338,11 +1338,10 @@ static void assert_plane(struct drm_i915_private *dev_priv, > static void assert_planes_disabled(struct drm_i915_private *dev_priv, > enum pipe pipe) > { > - struct drm_device *dev = dev_priv->dev; > int i; > > /* Primary planes are fixed to pipes on gen4+ */ > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > u32 val = I915_READ(DSPCNTR(pipe)); > I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, > "plane %c assertion failure, should be disabled but not\n", > @@ -1367,7 +1366,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, > struct drm_device *dev = dev_priv->dev; > int sprite; > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > for_each_sprite(dev_priv, pipe, sprite) { > u32 val = I915_READ(PLANE_CTL(pipe, sprite)); > I915_STATE_WARN(val & PLANE_CTL_ENABLE, > @@ -1381,12 +1380,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > sprite_name(pipe, sprite), pipe_name(pipe)); > } > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_GEN(dev_priv) >= 7) { > u32 val = I915_READ(SPRCTL(pipe)); > I915_STATE_WARN(val & SPRITE_ENABLE, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > plane_name(pipe), pipe_name(pipe)); > - } else if (INTEL_INFO(dev)->gen >= 5) { > + } else if (INTEL_GEN(dev_priv) >= 5) { > u32 val = I915_READ(DVSCNTR(pipe)); > I915_STATE_WARN(val & DVS_ENABLE, > "sprite %c assertion failure, should be off on pipe %c but is still active\n", > @@ -1685,7 +1684,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) > POSTING_READ(reg); > udelay(150); > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > I915_WRITE(DPLL_MD(crtc->pipe), > crtc->config->dpll_hw_state.dpll_md); > } else { > @@ -2660,7 +2659,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > > dspcntr |= DISPLAY_PLANE_ENABLE; > > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > if (intel_crtc->pipe == PIPE_B) > dspcntr |= DISPPLANE_SEL_PIPE_B; > > @@ -2705,7 +2704,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > BUG(); > } > > - if (INTEL_INFO(dev)->gen >= 4 && > + if (INTEL_GEN(dev_priv) >= 4 && > obj->tiling_mode != I915_TILING_NONE) > dspcntr |= DISPPLANE_TILED; > > @@ -2714,7 +2713,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > > linear_offset = y * fb->pitches[0] + x * cpp; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > intel_crtc->dspaddr_offset = > intel_compute_tile_offset(&x, &y, fb, 0, > fb->pitches[0], rotation); > @@ -2742,7 +2741,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, > I915_WRITE(reg, dspcntr); > > I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > I915_WRITE(DSPSURF(plane), > i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); > I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); > @@ -3256,7 +3255,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, > (pipe_config->pipe_src_h - 1)); > > /* on skylake this is done by detaching scalers */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > skl_detach_scalers(crtc); > > if (pipe_config->pch_pfit.enabled) > @@ -4888,7 +4887,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > if (!intel_crtc->config->has_dsi_encoder) > intel_ddi_enable_pipe_clock(intel_crtc); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > skylake_pfit_enable(intel_crtc); > else > ironlake_pfit_enable(intel_crtc); > @@ -5051,7 +5050,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) > if (!intel_crtc->config->has_dsi_encoder) > intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > skylake_scaler_disable(intel_crtc); > else > ironlake_pfit_disable(intel_crtc, false); > @@ -6629,7 +6628,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; > int clock_limit = dev_priv->max_dotclk_freq; > > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > clock_limit = dev_priv->max_cdclk_freq * 9 / 10; > > /* > @@ -6663,7 +6662,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > /* Cantiga+ cannot handle modes with a hsync front porch of 0. > * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. > */ > - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && > + if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev)) && > adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) > return -EINVAL; > > @@ -7227,7 +7226,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > int pipe = crtc->pipe; > enum transcoder transcoder = crtc->config->cpu_transcoder; > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_GEN(dev_priv) >= 5) { > I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); > I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); > I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); > @@ -7236,7 +7235,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > * for gen < 8) and if DRRS is supported (to make sure the > * registers are not unnecessarily accessed). > */ > - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && > + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_GEN(dev_priv) < 8) && > crtc->config->has_drrs) { > I915_WRITE(PIPE_DATA_M2(transcoder), > TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); > @@ -7626,7 +7625,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, > dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; > break; > } > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); > > if (crtc_state->sdvo_tv_clock) > @@ -7640,7 +7639,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, > dpll |= DPLL_VCO_ENABLE; > crtc_state->dpll_hw_state.dpll = dpll; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > u32 dpll_md = (crtc_state->pixel_multiplier - 1) > << DPLL_MD_UDI_MULTIPLIER_SHIFT; > crtc_state->dpll_hw_state.dpll_md = dpll_md; > @@ -7713,7 +7712,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) > vsyncshift += adjusted_mode->crtc_htotal; > } > > - if (INTEL_INFO(dev)->gen > 3) > + if (INTEL_GEN(dev_priv) > 3) > I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); > > I915_WRITE(HTOTAL(cpu_transcoder), > @@ -7882,7 +7881,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) > } > > if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { > - if (INTEL_INFO(dev)->gen < 4 || > + if (INTEL_GEN(dev_priv) < 4 || > intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) > pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; > else > @@ -8094,7 +8093,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = dev->dev_private; > uint32_t tmp; > > - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > + if (INTEL_GEN(dev_priv) <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) > return; > > tmp = I915_READ(PFIT_CONTROL); > @@ -8102,7 +8101,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, > return; > > /* Check whether the pfit is attached to our pipe. */ > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > if (crtc->pipe != PIPE_B) > return; > } else { > @@ -8166,7 +8165,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, > > fb = &intel_fb->base; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > if (val & DISPPLANE_TILED) { > plane_config->tiling = I915_TILING_X; > fb->modifier[0] = I915_FORMAT_MOD_X_TILED; > @@ -8178,7 +8177,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, > fb->pixel_format = fourcc; > fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > if (plane_config->tiling) > offset = I915_READ(DSPTILEOFF(plane)); > else > @@ -8286,7 +8285,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > (tmp & PIPECONF_COLOR_RANGE_SELECT)) > pipe_config->limited_color_range = true; > > - if (INTEL_INFO(dev)->gen < 4) > + if (INTEL_GEN(dev_priv) < 4) > pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; > > intel_get_pipe_timings(crtc, pipe_config); > @@ -8294,7 +8293,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > > i9xx_get_pfit_config(crtc, pipe_config); > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > /* No way to read it out on pipes B and C */ > if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) > tmp = dev_priv->chv_dpll_md[crtc->pipe]; > @@ -9074,7 +9073,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, > struct drm_i915_private *dev_priv = dev->dev_private; > enum pipe pipe = crtc->pipe; > > - if (INTEL_INFO(dev)->gen >= 5) { > + if (INTEL_GEN(dev_priv) >= 5) { > m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); > m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); > m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) > @@ -9086,7 +9085,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, > * gen < 8) and if DRRS is supported (to make sure the > * registers are not unnecessarily read). > */ > - if (m2_n2 && INTEL_INFO(dev)->gen < 8 && > + if (m2_n2 && INTEL_GEN(dev_priv) < 8 && > crtc->config->has_drrs) { > m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); > m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); > @@ -9288,7 +9287,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, > > fb = &intel_fb->base; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > if (val & DISPPLANE_TILED) { > plane_config->tiling = I915_TILING_X; > fb->modifier[0] = I915_FORMAT_MOD_X_TILED; > @@ -10110,7 +10109,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > * DDI E. So just check whether this pipe is wired to DDI E and whether > * the PCH transcoder is on. > */ > - if (INTEL_INFO(dev)->gen < 9 && > + if (INTEL_GEN(dev_priv) < 9 && > (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { > pipe_config->has_pch_encoder = true; > > @@ -10161,11 +10160,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > pipe_config->gamma_mode = > I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > skl_init_scalers(dev, crtc, pipe_config); > } > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > pipe_config->scaler_state.scaler_id = -1; > pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); > } > @@ -10173,7 +10172,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); > if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { > power_domain_mask |= BIT(power_domain); > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > skylake_get_pfit_config(crtc, pipe_config); > else > ironlake_get_pfit_config(crtc, pipe_config); > @@ -11046,7 +11045,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc, > * really needed there. But since ctg has the registers, > * include it in the check anyway. > */ > - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) > + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev)) > return true; > > /* > @@ -11653,7 +11652,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > * TILEOFF/LINOFF registers can't be changed via MI display flips. > * Note that pitch changes could also affect these register. > */ > - if (INTEL_INFO(dev)->gen > 3 && > + if (INTEL_GEN(dev_priv) > 3 && > (fb->offsets[0] != crtc->primary->fb->offsets[0] || > fb->pitches[0] != crtc->primary->fb->pitches[0])) > return -EINVAL; > @@ -11720,7 +11719,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > > atomic_inc(&intel_crtc->unpin_work_count); > > - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) > + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev)) > work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; > > if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { > @@ -11730,7 +11729,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, > engine = NULL; > } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { > engine = &dev_priv->engine[BCS]; > - } else if (INTEL_INFO(dev)->gen >= 7) { > + } else if (INTEL_GEN(dev_priv) >= 7) { > engine = i915_gem_request_get_engine(obj->last_write_req); > if (engine == NULL || engine->id != RCS) > engine = &dev_priv->engine[BCS]; > @@ -11919,7 +11918,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, > struct drm_framebuffer *fb = plane_state->fb; > int ret; > > - if (crtc_state && INTEL_INFO(dev)->gen >= 9 && > + if (crtc_state && INTEL_GEN(dev_priv) >= 9 && > plane->type != DRM_PLANE_TYPE_CURSOR) { > ret = skl_update_scaler_plane( > to_intel_crtc_state(crtc_state), > @@ -11987,7 +11986,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, > > /* Pre-gen9 platforms need two-step watermark updates */ > if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && > - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) > + INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) > to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; > > if (visible || was_visible) > @@ -12123,7 +12122,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, > pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; > } > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > if (mode_changed) > ret = skl_update_scaler_crtc(pipe_config); > > @@ -12928,7 +12927,7 @@ static void verify_wm_state(struct drm_crtc *crtc, > const enum pipe pipe = intel_crtc->pipe; > int plane; > > - if (INTEL_INFO(dev)->gen < 9 || !new_state->active) > + if (INTEL_GEN(dev_priv) < 9 || !new_state->active) > return; > > skl_ddb_get_hw_state(dev_priv, &hw_ddb); > @@ -14446,7 +14445,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > crtc_state->base.crtc = &intel_crtc->base; > > /* initialize shared scalers */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > if (pipe == PIPE_C) > intel_crtc->num_scalers = 1; > else > @@ -14475,7 +14474,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) > */ > intel_crtc->pipe = pipe; > intel_crtc->plane = pipe; > - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { > + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) < 4) { > DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); > intel_crtc->plane = !pipe; > } > @@ -14575,7 +14574,7 @@ static bool intel_crt_present(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > return false; > > if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) > @@ -14892,7 +14891,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > switch (mode_cmd->modifier[0]) { > case I915_FORMAT_MOD_Y_TILED: > case I915_FORMAT_MOD_Yf_TILED: > - if (INTEL_INFO(dev)->gen < 9) { > + if (INTEL_GEN(dev_priv) < 9) { > DRM_DEBUG("Unsupported tiling 0x%llx!\n", > mode_cmd->modifier[0]); > return -EINVAL; > @@ -14940,7 +14939,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_ARGB8888: > break; > case DRM_FORMAT_XRGB1555: > - if (INTEL_INFO(dev)->gen > 3) { > + if (INTEL_GEN(dev_priv) > 3) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14948,7 +14947,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > break; > case DRM_FORMAT_ABGR8888: > if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && > - INTEL_INFO(dev)->gen < 9) { > + INTEL_GEN(dev_priv) < 9) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14957,7 +14956,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_XBGR2101010: > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -14974,7 +14973,7 @@ static int intel_framebuffer_init(struct drm_device *dev, > case DRM_FORMAT_UYVY: > case DRM_FORMAT_YVYU: > case DRM_FORMAT_VYUY: > - if (INTEL_INFO(dev)->gen < 5) { > + if (INTEL_GEN(dev_priv) < 5) { > DRM_DEBUG("unsupported pixel format: %s\n", > drm_get_format_name(mode_cmd->pixel_format)); > return -EINVAL; > @@ -15747,7 +15746,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) > /* We need to sanitize the plane -> pipe mapping first because this will > * disable the crtc (and hence change the state) if it is wrong. Note > * that gen4+ has a fixed plane -> pipe mapping. */ > - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { > + if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { > bool plane; > > DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", > @@ -16278,7 +16277,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, > int intel_modeset_vga_set_state(struct drm_device *dev, bool state) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; > + unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; > u16 gmch_ctrl; > > if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { > @@ -16453,13 +16452,13 @@ struct intel_display_error_state * > err_printf(m, "Plane [%d]:\n", i); > err_printf(m, " CNTR: %08x\n", error->plane[i].control); > err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); > - if (INTEL_INFO(dev)->gen <= 3) { > + if (INTEL_GEN(dev_priv) <= 3) { > err_printf(m, " SIZE: %08x\n", error->plane[i].size); > err_printf(m, " POS: %08x\n", error->plane[i].pos); > } > - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) > + if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev)) > err_printf(m, " ADDR: %08x\n", error->plane[i].addr); > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > err_printf(m, " SURF: %08x\n", error->plane[i].surface); > err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); > } > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index f97cd53..72c869b 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1467,7 +1467,7 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, > intel_fixed_panel_mode(intel_connector->panel.fixed_mode, > adjusted_mode); > > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > int ret; > ret = skl_update_scaler_crtc(pipe_config); > if (ret) > @@ -2839,7 +2839,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder) > > if (IS_BROXTON(dev)) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; > - else if (INTEL_INFO(dev)->gen >= 9) { > + else if (INTEL_GEN(dev_priv) >= 9) { > if (dev_priv->vbt.edp.low_vswing && port == PORT_A) > return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; > return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; > @@ -3396,7 +3396,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) > DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); > } > > - if (INTEL_INFO(dev)->gen >= 9 && > + if (INTEL_GEN(dev_priv) >= 9 && > (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { > uint8_t frame_sync_cap; > > @@ -4671,7 +4671,7 @@ bool intel_dp_is_edp(struct drm_device *dev, enum port port) > * eDP not supported on g4x. so bail out early just > * for a bit extra safety in case the VBT is bonkers. > */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_GEN(dev_priv) < 5) > return false; > > if (port == PORT_A) > @@ -4985,7 +4985,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > return; > } > > - if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { > + if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev)) { > switch (index) { > case DRRS_HIGH_RR: > intel_dp_set_m_n(intel_crtc, M1_N1); > @@ -4997,7 +4997,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) > default: > DRM_ERROR("Unsupported refreshrate type\n"); > } > - } else if (INTEL_INFO(dev)->gen > 6) { > + } else if (INTEL_GEN(dev_priv) > 6) { > i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); > u32 val; > > @@ -5274,7 +5274,7 @@ void intel_edp_drrs_flush(struct drm_device *dev, > INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); > mutex_init(&dev_priv->drrs.mutex); > > - if (INTEL_INFO(dev)->gen <= 6) { > + if (INTEL_GEN(dev_priv) <= 6) { > DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); > return NULL; > } > @@ -5429,7 +5429,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > intel_dp->pps_pipe = INVALID_PIPE; > > /* intel_dp vfuncs */ > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; > else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) > intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; > @@ -5438,7 +5438,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, > else > intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; > else > intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; > @@ -5615,7 +5615,7 @@ bool intel_dp_init(struct drm_device *dev, > } else { > intel_encoder->pre_enable = g4x_pre_enable_dp; > intel_encoder->enable = g4x_enable_dp; > - if (INTEL_INFO(dev)->gen >= 5) > + if (INTEL_GEN(dev_priv) >= 5) > intel_encoder->post_disable = ilk_post_disable_dp; > } > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index c0eff15..fce4052 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -156,7 +156,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) > unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); > > /* PCH only available on ILK+ */ > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_GEN(dev_priv) < 5) > return; > > if (pll == NULL) > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index 62eaa89..ae19a62 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -122,12 +122,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, > > pipe_config->base.adjusted_mode.flags |= flags; > > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_GEN(dev_priv) < 5) > pipe_config->gmch_pfit.lvds_border_bits = > tmp & LVDS_BORDER_ENABLE; > > /* gen2/3 store dither state in pfit control, needs to match */ > - if (INTEL_INFO(dev)->gen < 4) { > + if (INTEL_GEN(dev_priv) < 4) { > tmp = I915_READ(PFIT_CONTROL); > > pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 658a756..6e0a6d9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2155,14 +2155,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) > wm[2] = (sskpd >> 12) & 0xFF; > wm[3] = (sskpd >> 20) & 0x1FF; > wm[4] = (sskpd >> 32) & 0x1FF; > - } else if (INTEL_INFO(dev)->gen >= 6) { > + } else if (INTEL_GEN(dev_priv) >= 6) { > uint32_t sskpd = I915_READ(MCH_SSKPD); > > wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; > wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; > wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; > wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; > - } else if (INTEL_INFO(dev)->gen >= 5) { > + } else if (INTEL_GEN(dev_priv) >= 5) { > uint32_t mltr = I915_READ(MLTR_ILK); > > /* ILK primary LP0 latency is 700 ns */ > @@ -2367,7 +2367,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) > usable_level = max_level; > > /* ILK/SNB: LP2+ watermarks only w/o sprites */ > - if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled) > + if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) > usable_level = 1; > > /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ > @@ -2510,12 +2510,12 @@ static void ilk_wm_merge(struct drm_device *dev, > int last_enabled_level = max_level; > > /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ > - if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && > + if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev)) && > config->num_pipes_active > 1) > last_enabled_level = 0; > > /* ILK: FBC WM must be disabled always */ > - merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; > + merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; > > /* merge each WM1+ level */ > for (level = 1; level <= max_level; level++) { > @@ -2821,7 +2821,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, > previous->wm_lp_spr[0] != results->wm_lp_spr[0]) > I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); > > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_GEN(dev_priv) >= 7) { > if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) > I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); > if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) > @@ -4056,7 +4056,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) > ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); > > /* 5/6 split only in single pipe config on IVB+ */ > - if (INTEL_INFO(dev)->gen >= 7 && > + if (INTEL_GEN(dev_priv) >= 7 && > config.num_pipes_active == 1 && config.sprites_enabled) { > ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); > ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); > @@ -4435,7 +4435,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) > hw->wm_lp[2] = I915_READ(WM3_LP_ILK); > > hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); > - if (INTEL_INFO(dev)->gen >= 7) { > + if (INTEL_GEN(dev_priv) >= 7) { > hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); > hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); > } > @@ -7537,7 +7537,7 @@ void intel_init_pm(struct drm_device *dev) > i915_ironlake_get_mem_freq(dev); > > /* For FIFO watermark updates */ > - if (INTEL_INFO(dev)->gen >= 9) { > + if (INTEL_GEN(dev_priv) >= 9) { > skl_setup_wm_latency(dev); > dev_priv->display.update_wm = skl_update_wm; > dev_priv->display.compute_global_watermarks = skl_compute_wm; > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 29a09bf..3d9b67a 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -455,7 +455,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) > /* Enable PSR on the panel */ > hsw_psr_enable_sink(intel_dp); > > - if (INTEL_INFO(dev)->gen >= 9) > + if (INTEL_GEN(dev_priv) >= 9) > intel_psr_activate(intel_dp); > } else { > vlv_psr_setup_vsc(intel_dp); > @@ -481,7 +481,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) > * - On HSW/BDW we get a recoverable frozen screen until next > * exit-activate sequence. > */ > - if (INTEL_INFO(dev)->gen < 9) > + if (INTEL_GEN(dev_priv) < 9) > schedule_delayed_work(&dev_priv->psr.work, > msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); > > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c > index 1a71456..f4e1b74 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -1271,13 +1271,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > return; > > /* Set the SDVO control regs. */ > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > /* The real mode polarity is set by the SDVO commands, using > * struct intel_sdvo_dtd. */ > sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; > if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) > sdvox |= HDMI_COLOR_RANGE_16_235; > - if (INTEL_INFO(dev)->gen < 5) > + if (INTEL_GEN(dev_priv) < 5) > sdvox |= SDVO_BORDER_ENABLE; > } else { > sdvox = I915_READ(intel_sdvo->sdvo_reg); > @@ -1296,7 +1296,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > if (intel_sdvo->has_hdmi_audio) > sdvox |= SDVO_AUDIO_ENABLE; > > - if (INTEL_INFO(dev)->gen >= 4) { > + if (INTEL_GEN(dev_priv) >= 4) { > /* done in crtc_mode_set as the dpll_md reg must be written early */ > } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { > /* done in crtc_mode_set as it lives inside the dpll register */ > @@ -1306,7 +1306,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) > } > > if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && > - INTEL_INFO(dev)->gen < 5) > + INTEL_GEN(dev_priv) < 5) > sdvox |= SDVO_STALL_SELECT; > intel_sdvo_write_sdvox(intel_sdvo, sdvox); > } > diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c > index 1f3a0e1..71a65ef 100644 > --- a/drivers/gpu/drm/i915/intel_tv.c > +++ b/drivers/gpu/drm/i915/intel_tv.c > @@ -1099,7 +1099,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder) > > set_color_conversion(dev_priv, color_conversion); > > - if (INTEL_INFO(dev)->gen >= 4) > + if (INTEL_GEN(dev_priv) >= 4) > I915_WRITE(TV_CLR_KNOBS, 0x00404000); > else > I915_WRITE(TV_CLR_KNOBS, 0x00606000); > A few instances of the small comment I made above, which I think would be a good opportunity. Otherwise all looks OK. Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> But needs more acks, since last time we discussed this conclusion was it was too much disruption for the benefit. Regards, Tvrtko
On 13/06/16 10:28, Tvrtko Ursulin wrote: > > On 10/06/16 18:35, Dave Gordon wrote: >> More Coccinellery ... >> >> Wherever we find "INTEL_INFO(dev)->gen", and have a suitable >> "dev_priv" in scope, replace it with "INTEL_GEN(dev_priv)". >> At this time, we've found 189 instances, and each replacement >> saves one memory cycle at runtime and two bytes of codespace >> (~360 bytes total text size reduction). >> >> @dev_priv_param@ >> function FUNC; >> idexpression struct drm_device *DEV; >> identifier DEV_PRIV; >> @@ >> FUNC(..., struct drm_i915_private *DEV_PRIV, ...) >> { >> <... >> - INTEL_INFO(DEV)->gen >> + INTEL_GEN(DEV_PRIV) >> ...> >> } >> >> @dev_priv_local@ >> idexpression struct drm_device *DEV; >> identifier DEV_PRIV; >> expression E; >> @@ >> { >> ... >> ( >> struct drm_i915_private *DEV_PRIV; >> | >> struct drm_i915_private *DEV_PRIV = E; >> ) >> <... >> - INTEL_INFO(DEV)->gen >> + INTEL_GEN(DEV_PRIV) >> ...> >> } >> >> Plus manual deletion of one now-unused local "dev". >> >> Signed-off-by: Dave Gordon <david.s.gordon@intel.com> >> --- >> drivers/gpu/drm/i915/i915_debugfs.c | 52 +++++++------- >> drivers/gpu/drm/i915/i915_dma.c | 16 ++--- >> drivers/gpu/drm/i915/i915_drv.c | 2 +- >> drivers/gpu/drm/i915/i915_gem.c | 4 +- >> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-- >> drivers/gpu/drm/i915/i915_gem_fence.c | 8 +-- >> drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- >> drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- >> drivers/gpu/drm/i915/i915_gpu_error.c | 14 ++-- >> drivers/gpu/drm/i915/i915_irq.c | 12 ++-- >> drivers/gpu/drm/i915/i915_suspend.c | 20 +++--- >> drivers/gpu/drm/i915/intel_color.c | 2 +- >> drivers/gpu/drm/i915/intel_crt.c | 6 +- >> drivers/gpu/drm/i915/intel_ddi.c | 4 +- >> drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++--------------- >> drivers/gpu/drm/i915/intel_dp.c | 20 +++--- >> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- >> drivers/gpu/drm/i915/intel_lvds.c | 4 +- >> drivers/gpu/drm/i915/intel_pm.c | 18 ++--- >> drivers/gpu/drm/i915/intel_psr.c | 4 +- >> drivers/gpu/drm/i915/intel_sdvo.c | 8 +-- >> drivers/gpu/drm/i915/intel_tv.c | 2 +- >> 22 files changed, 167 insertions(+), 168 deletions(-) [snip] >> @@ -553,7 +553,7 @@ void i915_gem_restore_fences(struct drm_device *dev) >> uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; >> uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; >> >> - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { >> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev)) { > > While we are churning :), could looks for both dev_priv and dev in the > same condition like here and tidy those. [snip] > A few instances of the small comment I made above, which I think would > be a good opportunity. Otherwise all looks OK. > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > But needs more acks, since last time we discussed this conclusion was it > was too much disruption for the benefit. > > Regards, > Tvrtko Yes, that's why this was a minimal set for replacement of one specific but very common idiom that has a definite benefit. At the other extreme, I have a Cocci patch to replace *all* INTEL_INFO()->gen with INTEL_GEN() and then replace the 'dev' parameter to INTEL_INFO(), INTEL_GEN() and all the IS_X() macros wherever possible; but that really is a lot of churn for proportionately less benefit. Or we could pick replacements on a file-by-file basis rather than according to which macro they use. Or maybe one patch each for the big targets (debugfs.c, display.c) and another one that does all the files where there are only a few lines of changes. Opinions, anybody? .Dave.
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e4f2c55..6a106d5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -672,7 +672,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) intel_crtc_get_vblank_counter(crtc)); seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); else addr = I915_READ(DSPADDR(crtc->plane)); @@ -869,7 +869,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GEN8_PCU_IIR)); seq_printf(m, "PCU interrupt enable:\t%08x\n", I915_READ(GEN8_PCU_IER)); - } else if (INTEL_INFO(dev)->gen >= 8) { + } else if (INTEL_GEN(dev_priv) >= 8) { seq_printf(m, "Master Interrupt Control:\t%08x\n", I915_READ(GEN8_MASTER_IRQ)); @@ -995,7 +995,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GTIMR)); } for_each_engine(engine, dev_priv) { - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", engine->name, I915_READ_IMR(engine)); @@ -1232,7 +1232,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq)); mutex_unlock(&dev_priv->rps.hw_lock); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_GEN(dev_priv) >= 6) { u32 rp_state_limits; u32 gt_perf_status; u32 rp_state_cap; @@ -1745,7 +1745,7 @@ static int i915_fbc_fc_get(void *data, u64 *val) struct drm_device *dev = data; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev)) return -ENODEV; *val = dev_priv->fbc.false_color; @@ -1759,7 +1759,7 @@ static int i915_fbc_fc_set(void *data, u64 val) struct drm_i915_private *dev_priv = dev->dev_private; u32 reg; - if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev)) + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev)) return -ENODEV; mutex_lock(&dev_priv->fbc.lock); @@ -1795,7 +1795,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) seq_printf(m, "Enabled by kernel parameter: %s\n", yesno(i915.enable_ips)); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { seq_puts(m, "Currently: unknown\n"); } else { if (I915_READ(IPS_CTL) & IPS_ENABLE) @@ -2266,7 +2266,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ16(C0DRB3)); seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_GEN(dev_priv) >= 6) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", I915_READ(MAD_DIMM_C0)); seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", @@ -2275,7 +2275,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ(MAD_DIMM_C2)); seq_printf(m, "TILECTL = 0x%08x\n", I915_READ(TILECTL)); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) seq_printf(m, "GAMTARBMODE = 0x%08x\n", I915_READ(GAMTARBMODE)); else @@ -2380,9 +2380,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) return ret; intel_runtime_pm_get(dev_priv); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) gen8_ppgtt_info(m, dev); - else if (INTEL_INFO(dev)->gen >= 6) + else if (INTEL_GEN(dev_priv) >= 6) gen6_ppgtt_info(m, dev); mutex_lock(&dev->filelist_mutex); @@ -2741,7 +2741,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data) u64 power; u32 units; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -3338,7 +3338,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) enum pipe pipe; int plane; - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_GEN(dev_priv) < 9) return 0; drm_modeset_lock_all(dev); @@ -4091,7 +4091,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, if (IS_GEN2(dev)) ret = i8xx_pipe_crc_ctl_reg(&source, &val); - else if (INTEL_INFO(dev)->gen < 5) + else if (INTEL_GEN(dev_priv) < 5) ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val); else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val); @@ -4578,7 +4578,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.pri_latency; @@ -4594,7 +4594,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.spr_latency; @@ -4610,7 +4610,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = dev->dev_private; const uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.cur_latency; @@ -4701,7 +4701,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.pri_latency; @@ -4717,7 +4717,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.spr_latency; @@ -4733,7 +4733,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; uint16_t *latencies; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) latencies = dev_priv->wm.skl_latency; else latencies = to_i915(dev)->wm.cur_latency; @@ -4973,7 +4973,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -4996,7 +4996,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, u32 hw_max, hw_min; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -5040,7 +5040,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = dev->dev_private; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -5063,7 +5063,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, u32 hw_max, hw_min; int ret; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return -ENODEV; flush_delayed_work(&dev_priv->rps.delayed_resume_work); @@ -5341,7 +5341,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) struct drm_device *dev = inode->i_private; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return 0; intel_runtime_pm_get(dev_priv); @@ -5355,7 +5355,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) struct drm_device *dev = inode->i_private; struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return 0; intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 07edaed..afd4598 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -165,7 +165,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_HAS_EXEC_CONSTANTS: - value = INTEL_INFO(dev)->gen >= 4; + value = INTEL_GEN(dev_priv) >= 4; break; case I915_PARAM_HAS_RELAXED_DELTA: value = 1; @@ -261,12 +261,12 @@ static int i915_get_bridge_dev(struct drm_device *dev) intel_alloc_mchbar_resource(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret; - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; @@ -293,7 +293,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) return ret; } - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); @@ -307,7 +307,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) intel_setup_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool enabled; @@ -347,7 +347,7 @@ static int i915_get_bridge_dev(struct drm_device *dev) intel_teardown_mchbar(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; if (dev_priv->mchbar_need_disable) { if (IS_I915G(dev) || IS_I915GM(dev)) { @@ -948,7 +948,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev) cherryview_sseu_info_init(dev); else if (IS_BROADWELL(dev)) broadwell_sseu_info_init(dev); - else if (INTEL_INFO(dev)->gen >= 9) + else if (INTEL_GEN(dev_priv) >= 9) gen9_sseu_info_init(dev); info->has_snoop = !info->has_llc; @@ -1143,7 +1143,7 @@ static int i915_mmio_setup(struct drm_device *dev) * the register BAR remains the same size for all the earlier * generations up to Ironlake. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) mmio_size = 512 * 1024; else mmio_size = 2 * 1024 * 1024; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 872c6060..97ddba5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -998,7 +998,7 @@ int i915_reset(struct drm_i915_private *dev_priv) * previous concerns that it doesn't respond well to some forms * of re-init after reset. */ - if (INTEL_INFO(dev)->gen > 5) + if (INTEL_GEN(dev_priv) > 5) intel_enable_gt_powersave(dev_priv); return 0; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index eae8d7a..4aeee79 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4778,7 +4778,7 @@ void i915_gem_init_swizzling(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen < 5 || + if (INTEL_GEN(dev_priv) < 5 || dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; @@ -4895,7 +4895,7 @@ int i915_gem_init_engines(struct drm_device *dev) u32 temp = I915_READ(GEN7_MSG_CTL); temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); I915_WRITE(GEN7_MSG_CTL, temp); - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); temp &= ~RESET_PCH_HANDSHAKE_ENABLE; I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 8097698..86e052c 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -335,7 +335,7 @@ static inline uint64_t gen8_noncanonical_addr(uint64_t address) offset & PAGE_MASK); iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { offset += sizeof(uint32_t); if (offset_in_page(offset) == 0) { @@ -1254,19 +1254,19 @@ static bool only_mappable_for_reloc(unsigned int flags) } if (instp_mode != dev_priv->relative_constants_mode) { - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { DRM_DEBUG("no rel constants on pre-gen4\n"); return -EINVAL; } - if (INTEL_INFO(dev)->gen > 5 && + if (INTEL_GEN(dev_priv) > 5 && instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); return -EINVAL; } /* The HW changed the meaning on this bit on gen6 */ - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_GEN(dev_priv) >= 6) instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; } break; diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c index 2b6bdc2..013e69c 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence.c @@ -62,7 +62,7 @@ static void i965_write_fence_reg(struct drm_device *dev, int reg, i915_reg_t fence_reg_lo, fence_reg_hi; int fence_pitch_shift; - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { fence_reg_lo = FENCE_REG_GEN6_LO(reg); fence_reg_hi = FENCE_REG_GEN6_HI(reg); fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; @@ -209,7 +209,7 @@ static void i915_gem_write_fence(struct drm_device *dev, int reg, i830_write_fence_reg(dev, reg, obj); else if (IS_GEN3(dev)) i915_write_fence_reg(dev, reg, obj); - else if (INTEL_INFO(dev)->gen >= 4) + else if (INTEL_GEN(dev_priv) >= 4) i965_write_fence_reg(dev, reg, obj); /* And similarly be paranoid that no direct access to this region @@ -553,7 +553,7 @@ void i915_gem_restore_fences(struct drm_device *dev) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) { + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev)) { /* * On BDW+, swizzling is not used. We leave the CPU memory * controller in charge of optimizing memory accesses without @@ -563,7 +563,7 @@ void i915_gem_restore_fences(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_GEN(dev_priv) >= 6) { if (dev_priv->preserve_bios_swizzle) { if (I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4668477..ac860af 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2324,7 +2324,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) /* Don't bother messing with faults pre GEN6 as we have little * documentation supporting that it's a good idea. */ - if (INTEL_INFO(dev)->gen < 6) + if (INTEL_GEN(dev_priv) < 6) return; i915_check_and_clear_faults(dev_priv); @@ -3054,7 +3054,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl); } else if (IS_CHERRYVIEW(dev)) { @@ -3173,10 +3173,10 @@ int i915_ggtt_init_hw(struct drm_device *dev) struct i915_ggtt *ggtt = &dev_priv->ggtt; int ret; - if (INTEL_INFO(dev)->gen <= 5) { + if (INTEL_GEN(dev_priv) <= 5) { ggtt->probe = i915_gmch_probe; ggtt->base.cleanup = i915_gmch_remove; - } else if (INTEL_INFO(dev)->gen < 8) { + } else if (INTEL_GEN(dev_priv) < 8) { ggtt->probe = gen6_gmch_probe; ggtt->base.cleanup = gen6_gmch_remove; @@ -3186,7 +3186,7 @@ int i915_ggtt_init_hw(struct drm_device *dev) ggtt->base.pte_encode = hsw_pte_encode; else if (IS_VALLEYVIEW(dev)) ggtt->base.pte_encode = byt_pte_encode; - else if (INTEL_INFO(dev)->gen >= 7) + else if (INTEL_GEN(dev_priv) >= 7) ggtt->base.pte_encode = ivb_pte_encode; else ggtt->base.pte_encode = snb_pte_encode; @@ -3271,7 +3271,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); } - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) chv_setup_private_ppat(dev_priv); else diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index e9cd822..7b8383e 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -108,7 +108,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) * */ base = 0; - if (INTEL_INFO(dev)->gen >= 3) { + if (INTEL_GEN(dev_priv) >= 3) { u32 bsm; pci_read_config_dword(dev->pdev, INTEL_BSM, &bsm); @@ -192,7 +192,7 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) return 0; /* make sure we don't clobber the GTT if it's within stolen memory */ - if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { + if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev) && !IS_G4X(dev)) { struct { u32 start, end; } stolen[2] = { @@ -405,7 +405,7 @@ int i915_gem_init_stolen(struct drm_device *dev) mutex_init(&dev_priv->mm.stolen_lock); #ifdef CONFIG_INTEL_IOMMU - if (intel_iommu_gfx_mapped && INTEL_INFO(dev)->gen < 8) { + if (intel_iommu_gfx_mapped && INTEL_GEN(dev_priv) < 8) { DRM_INFO("DMAR active, disabling use of stolen memory\n"); return 0; } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 34ff245..1da09c5 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -382,7 +382,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "EIR: 0x%08x\n", error->eir); err_printf(m, "IER: 0x%08x\n", error->ier); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { for (i = 0; i < 4; i++) err_printf(m, "GTIER gt %d: 0x%08x\n", i, error->gtier[i]); @@ -401,10 +401,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, " INSTDONE_%d: 0x%08x\n", i, error->extra_instdone[i]); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { err_printf(m, "ERROR: 0x%08x\n", error->error); - if (INTEL_INFO(dev)->gen >= 8) + if (INTEL_GEN(dev_priv) >= 8) err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", error->fault_data1, error->fault_data0); @@ -1251,7 +1251,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (IS_GEN7(dev)) error->err_int = I915_READ(GEN7_ERR_INT); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } @@ -1263,10 +1263,10 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, } /* 2: Registers which belong to multiple generations */ - if (INTEL_INFO(dev)->gen >= 7) + if (INTEL_GEN(dev_priv) >= 7) error->forcewake = I915_READ_FW(FORCEWAKE_MT); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { error->derrmr = I915_READ(DERRMR); error->error = I915_READ(ERROR_GEN6); error->done_reg = I915_READ(DONE_REG); @@ -1282,7 +1282,7 @@ static void i915_capture_reg_state(struct drm_i915_private *dev_priv, if (HAS_HW_CONTEXTS(dev)) error->ccid = I915_READ(CCID); - if (INTEL_INFO(dev)->gen >= 8) { + if (INTEL_GEN(dev_priv) >= 8) { error->ier = I915_READ(GEN8_DE_MISC_IER); for (i = 0; i < 4; i++) error->gtier[i] = I915_READ(GEN8_GT_IER(i)); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4378a65..2b7d292 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2729,7 +2729,7 @@ static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) unsigned long irqflags; spin_lock_irqsave(&dev_priv->irq_lock, irqflags); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) i915_enable_pipestat(dev_priv, pipe, PIPE_START_VBLANK_INTERRUPT_STATUS); else @@ -2744,7 +2744,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : + uint32_t bit = (INTEL_GEN(dev_priv) >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -2798,7 +2798,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; - uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : + uint32_t bit = (INTEL_GEN(dev_priv) >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -3303,7 +3303,7 @@ static void gen5_gt_irq_reset(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; GEN5_IRQ_RESET(GT); - if (INTEL_INFO(dev)->gen >= 6) + if (INTEL_GEN(dev_priv) >= 6) GEN5_IRQ_RESET(GEN6_PM); } @@ -3640,7 +3640,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); - if (INTEL_INFO(dev)->gen >= 6) { + if (INTEL_GEN(dev_priv) >= 6) { /* * RPS interrupts will get enabled/disabled on demand when RPS * itself is enabled/disabled. @@ -3658,7 +3658,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; u32 display_mask, extra_mask; - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | DE_PLANEB_FLIP_DONE_IVB | diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 34e061a..048a7e1 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -34,13 +34,13 @@ static void i915_save_display(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; /* Display arbitration control */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_GEN(dev_priv) <= 4) dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); /* LVDS state */ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) + else if (INTEL_GEN(dev_priv) <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) dev_priv->regfile.saveLVDS = I915_READ(LVDS); /* Panel power sequencer */ @@ -49,7 +49,7 @@ static void i915_save_display(struct drm_device *dev) dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); - } else if (INTEL_INFO(dev)->gen <= 4) { + } else if (INTEL_GEN(dev_priv) <= 4) { dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); @@ -57,7 +57,7 @@ static void i915_save_display(struct drm_device *dev) } /* save FBC interval */ - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev)) dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); } @@ -67,7 +67,7 @@ static void i915_restore_display(struct drm_device *dev) u32 mask = 0xffffffff; /* Display arbitration */ - if (INTEL_INFO(dev)->gen <= 4) + if (INTEL_GEN(dev_priv) <= 4) I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); mask = ~LVDS_PORT_EN; @@ -75,7 +75,7 @@ static void i915_restore_display(struct drm_device *dev) /* LVDS state */ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); - else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) + else if (INTEL_GEN(dev_priv) <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); /* Panel power sequencer */ @@ -84,7 +84,7 @@ static void i915_restore_display(struct drm_device *dev) I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); - } else if (INTEL_INFO(dev)->gen <= 4) { + } else if (INTEL_GEN(dev_priv) <= 4) { I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); @@ -95,7 +95,7 @@ static void i915_restore_display(struct drm_device *dev) intel_fbc_global_disable(dev_priv); /* restore FBC interval */ - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev)) + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev)) I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); i915_redisable_vga(dev); @@ -115,7 +115,7 @@ int i915_save_state(struct drm_device *dev) &dev_priv->regfile.saveGCDGMBUS); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_GEN(dev_priv) < 7) dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ @@ -161,7 +161,7 @@ int i915_restore_state(struct drm_device *dev) i915_restore_display(dev); /* Cache mode state */ - if (INTEL_INFO(dev)->gen < 7) + if (INTEL_GEN(dev_priv) < 7) I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 522f5a2..778dec1 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -179,7 +179,7 @@ static void i9xx_load_csc_matrix(struct drm_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); - if (INTEL_INFO(dev)->gen > 6) { + if (INTEL_GEN(dev_priv) > 6) { uint16_t postoff = 0; if (intel_crtc->config->limited_color_range) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 6229681..668f57e 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -152,7 +152,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; u32 adpa; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) adpa = ADPA_HOTPLUG_BITS; else adpa = 0; @@ -653,7 +653,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { if (intel_crt_detect_ddc(connector)) status = connector_status_connected; - else if (INTEL_INFO(dev)->gen < 4) + else if (INTEL_GEN(dev_priv) < 4) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); else if (i915.load_detect_test) @@ -719,7 +719,7 @@ static void intel_crt_reset(struct drm_connector *connector) struct drm_i915_private *dev_priv = dev->dev_private; struct intel_crt *crt = intel_attached_crt(connector); - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { u32 adpa; adpa = I915_READ(crt->adpa_reg); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 022b41d..71d8fb1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1671,7 +1671,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port))); - else if (INTEL_INFO(dev)->gen < 9) + else if (INTEL_GEN(dev_priv) < 9) I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); if (type == INTEL_OUTPUT_HDMI) { @@ -1705,7 +1705,7 @@ static void intel_enable_ddi(struct intel_encoder *intel_encoder) } else if (type == INTEL_OUTPUT_EDP) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - if (port == PORT_A && INTEL_INFO(dev)->gen < 9) + if (port == PORT_A && INTEL_GEN(dev_priv) < 9) intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(intel_dp); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 473c8fd..984b9fc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1120,7 +1120,7 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc) enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { i915_reg_t reg = PIPECONF(cpu_transcoder); /* Wait for the Pipe State to go off */ @@ -1338,11 +1338,10 @@ static void assert_plane(struct drm_i915_private *dev_priv, static void assert_planes_disabled(struct drm_i915_private *dev_priv, enum pipe pipe) { - struct drm_device *dev = dev_priv->dev; int i; /* Primary planes are fixed to pipes on gen4+ */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { u32 val = I915_READ(DSPCNTR(pipe)); I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, "plane %c assertion failure, should be disabled but not\n", @@ -1367,7 +1366,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, struct drm_device *dev = dev_priv->dev; int sprite; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { for_each_sprite(dev_priv, pipe, sprite) { u32 val = I915_READ(PLANE_CTL(pipe, sprite)); I915_STATE_WARN(val & PLANE_CTL_ENABLE, @@ -1381,12 +1380,12 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv, "sprite %c assertion failure, should be off on pipe %c but is still active\n", sprite_name(pipe, sprite), pipe_name(pipe)); } - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { u32 val = I915_READ(SPRCTL(pipe)); I915_STATE_WARN(val & SPRITE_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", plane_name(pipe), pipe_name(pipe)); - } else if (INTEL_INFO(dev)->gen >= 5) { + } else if (INTEL_GEN(dev_priv) >= 5) { u32 val = I915_READ(DVSCNTR(pipe)); I915_STATE_WARN(val & DVS_ENABLE, "sprite %c assertion failure, should be off on pipe %c but is still active\n", @@ -1685,7 +1684,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc) POSTING_READ(reg); udelay(150); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { I915_WRITE(DPLL_MD(crtc->pipe), crtc->config->dpll_hw_state.dpll_md); } else { @@ -2660,7 +2659,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, dspcntr |= DISPLAY_PLANE_ENABLE; - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { if (intel_crtc->pipe == PIPE_B) dspcntr |= DISPPLANE_SEL_PIPE_B; @@ -2705,7 +2704,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, BUG(); } - if (INTEL_INFO(dev)->gen >= 4 && + if (INTEL_GEN(dev_priv) >= 4 && obj->tiling_mode != I915_TILING_NONE) dspcntr |= DISPPLANE_TILED; @@ -2714,7 +2713,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, linear_offset = y * fb->pitches[0] + x * cpp; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { intel_crtc->dspaddr_offset = intel_compute_tile_offset(&x, &y, fb, 0, fb->pitches[0], rotation); @@ -2742,7 +2741,7 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, I915_WRITE(reg, dspcntr); I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { I915_WRITE(DSPSURF(plane), i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); @@ -3256,7 +3255,7 @@ static void intel_update_pipe_config(struct intel_crtc *crtc, (pipe_config->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { skl_detach_scalers(crtc); if (pipe_config->pch_pfit.enabled) @@ -4888,7 +4887,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) if (!intel_crtc->config->has_dsi_encoder) intel_ddi_enable_pipe_clock(intel_crtc); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_pfit_enable(intel_crtc); else ironlake_pfit_enable(intel_crtc); @@ -5051,7 +5050,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) if (!intel_crtc->config->has_dsi_encoder) intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(intel_crtc, false); @@ -6629,7 +6628,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int clock_limit = dev_priv->max_dotclk_freq; - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { clock_limit = dev_priv->max_cdclk_freq * 9 / 10; /* @@ -6663,7 +6662,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ - if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && + if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev)) && adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) return -EINVAL; @@ -7227,7 +7226,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, int pipe = crtc->pipe; enum transcoder transcoder = crtc->config->cpu_transcoder; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); @@ -7236,7 +7235,7 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, * for gen < 8) and if DRRS is supported (to make sure the * registers are not unnecessarily accessed). */ - if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && + if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { I915_WRITE(PIPE_DATA_M2(transcoder), TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); @@ -7626,7 +7625,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -7640,7 +7639,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLL_VCO_ENABLE; crtc_state->dpll_hw_state.dpll = dpll; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { u32 dpll_md = (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc_state->dpll_hw_state.dpll_md = dpll_md; @@ -7713,7 +7712,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) vsyncshift += adjusted_mode->crtc_htotal; } - if (INTEL_INFO(dev)->gen > 3) + if (INTEL_GEN(dev_priv) > 3) I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); I915_WRITE(HTOTAL(cpu_transcoder), @@ -7882,7 +7881,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) } if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (INTEL_INFO(dev)->gen < 4 || + if (INTEL_GEN(dev_priv) < 4 || intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; else @@ -8094,7 +8093,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; uint32_t tmp; - if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) + if (INTEL_GEN(dev_priv) <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) return; tmp = I915_READ(PFIT_CONTROL); @@ -8102,7 +8101,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, return; /* Check whether the pfit is attached to our pipe. */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { if (crtc->pipe != PIPE_B) return; } else { @@ -8166,7 +8165,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier[0] = I915_FORMAT_MOD_X_TILED; @@ -8178,7 +8177,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc, fb->pixel_format = fourcc; fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(plane)); else @@ -8286,7 +8285,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; - if (INTEL_INFO(dev)->gen < 4) + if (INTEL_GEN(dev_priv) < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; intel_get_pipe_timings(crtc, pipe_config); @@ -8294,7 +8293,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* No way to read it out on pipes B and C */ if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; @@ -9074,7 +9073,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = crtc->pipe; - if (INTEL_INFO(dev)->gen >= 5) { + if (INTEL_GEN(dev_priv) >= 5) { m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) @@ -9086,7 +9085,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, * gen < 8) and if DRRS is supported (to make sure the * registers are not unnecessarily read). */ - if (m2_n2 && INTEL_INFO(dev)->gen < 8 && + if (m2_n2 && INTEL_GEN(dev_priv) < 8 && crtc->config->has_drrs) { m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); @@ -9288,7 +9287,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, fb = &intel_fb->base; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier[0] = I915_FORMAT_MOD_X_TILED; @@ -10110,7 +10109,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - if (INTEL_INFO(dev)->gen < 9 && + if (INTEL_GEN(dev_priv) < 9 && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -10161,11 +10160,11 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { skl_init_scalers(dev, crtc, pipe_config); } - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { pipe_config->scaler_state.scaler_id = -1; pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); } @@ -10173,7 +10172,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT(power_domain); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -11046,7 +11045,7 @@ static bool __pageflip_finished_cs(struct intel_crtc *crtc, * really needed there. But since ctg has the registers, * include it in the check anyway. */ - if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev)) return true; /* @@ -11653,7 +11652,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. */ - if (INTEL_INFO(dev)->gen > 3 && + if (INTEL_GEN(dev_priv) > 3 && (fb->offsets[0] != crtc->primary->fb->offsets[0] || fb->pitches[0] != crtc->primary->fb->pitches[0])) return -EINVAL; @@ -11720,7 +11719,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, atomic_inc(&intel_crtc->unpin_work_count); - if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev)) work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { @@ -11730,7 +11729,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, engine = NULL; } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { engine = &dev_priv->engine[BCS]; - } else if (INTEL_INFO(dev)->gen >= 7) { + } else if (INTEL_GEN(dev_priv) >= 7) { engine = i915_gem_request_get_engine(obj->last_write_req); if (engine == NULL || engine->id != RCS) engine = &dev_priv->engine[BCS]; @@ -11919,7 +11918,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, struct drm_framebuffer *fb = plane_state->fb; int ret; - if (crtc_state && INTEL_INFO(dev)->gen >= 9 && + if (crtc_state && INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { ret = skl_update_scaler_plane( to_intel_crtc_state(crtc_state), @@ -11987,7 +11986,7 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, /* Pre-gen9 platforms need two-step watermark updates */ if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && - INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) + INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; if (visible || was_visible) @@ -12123,7 +12122,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; } - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -12928,7 +12927,7 @@ static void verify_wm_state(struct drm_crtc *crtc, const enum pipe pipe = intel_crtc->pipe; int plane; - if (INTEL_INFO(dev)->gen < 9 || !new_state->active) + if (INTEL_GEN(dev_priv) < 9 || !new_state->active) return; skl_ddb_get_hw_state(dev_priv, &hw_ddb); @@ -14446,7 +14445,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) crtc_state->base.crtc = &intel_crtc->base; /* initialize shared scalers */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { if (pipe == PIPE_C) intel_crtc->num_scalers = 1; else @@ -14475,7 +14474,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe) */ intel_crtc->pipe = pipe; intel_crtc->plane = pipe; - if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { + if (HAS_FBC(dev) && INTEL_GEN(dev_priv) < 4) { DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); intel_crtc->plane = !pipe; } @@ -14575,7 +14574,7 @@ static bool intel_crt_present(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) return false; if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) @@ -14892,7 +14891,7 @@ static int intel_framebuffer_init(struct drm_device *dev, switch (mode_cmd->modifier[0]) { case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_Yf_TILED: - if (INTEL_INFO(dev)->gen < 9) { + if (INTEL_GEN(dev_priv) < 9) { DRM_DEBUG("Unsupported tiling 0x%llx!\n", mode_cmd->modifier[0]); return -EINVAL; @@ -14940,7 +14939,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - if (INTEL_INFO(dev)->gen > 3) { + if (INTEL_GEN(dev_priv) > 3) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14948,7 +14947,7 @@ static int intel_framebuffer_init(struct drm_device *dev, break; case DRM_FORMAT_ABGR8888: if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && - INTEL_INFO(dev)->gen < 9) { + INTEL_GEN(dev_priv) < 9) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14957,7 +14956,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -14974,7 +14973,7 @@ static int intel_framebuffer_init(struct drm_device *dev, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: - if (INTEL_INFO(dev)->gen < 5) { + if (INTEL_GEN(dev_priv) < 5) { DRM_DEBUG("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format)); return -EINVAL; @@ -15747,7 +15746,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) /* We need to sanitize the plane -> pipe mapping first because this will * disable the crtc (and hence change the state) if it is wrong. Note * that gen4+ has a fixed plane -> pipe mapping. */ - if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { + if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { bool plane; DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", @@ -16278,7 +16277,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, int intel_modeset_vga_set_state(struct drm_device *dev, bool state) { struct drm_i915_private *dev_priv = dev->dev_private; - unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; + unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; u16 gmch_ctrl; if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { @@ -16453,13 +16452,13 @@ struct intel_display_error_state * err_printf(m, "Plane [%d]:\n", i); err_printf(m, " CNTR: %08x\n", error->plane[i].control); err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); - if (INTEL_INFO(dev)->gen <= 3) { + if (INTEL_GEN(dev_priv) <= 3) { err_printf(m, " SIZE: %08x\n", error->plane[i].size); err_printf(m, " POS: %08x\n", error->plane[i].pos); } - if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) + if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev)) err_printf(m, " ADDR: %08x\n", error->plane[i].addr); - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { err_printf(m, " SURF: %08x\n", error->plane[i].surface); err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index f97cd53..72c869b 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1467,7 +1467,7 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { int ret; ret = skl_update_scaler_crtc(pipe_config); if (ret) @@ -2839,7 +2839,7 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder) if (IS_BROXTON(dev)) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; - else if (INTEL_INFO(dev)->gen >= 9) { + else if (INTEL_GEN(dev_priv) >= 9) { if (dev_priv->vbt.edp.low_vswing && port == PORT_A) return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; @@ -3396,7 +3396,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); } - if (INTEL_INFO(dev)->gen >= 9 && + if (INTEL_GEN(dev_priv) >= 9 && (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { uint8_t frame_sync_cap; @@ -4671,7 +4671,7 @@ bool intel_dp_is_edp(struct drm_device *dev, enum port port) * eDP not supported on g4x. so bail out early just * for a bit extra safety in case the VBT is bonkers. */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) return false; if (port == PORT_A) @@ -4985,7 +4985,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) return; } - if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { + if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev)) { switch (index) { case DRRS_HIGH_RR: intel_dp_set_m_n(intel_crtc, M1_N1); @@ -4997,7 +4997,7 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) default: DRM_ERROR("Unsupported refreshrate type\n"); } - } else if (INTEL_INFO(dev)->gen > 6) { + } else if (INTEL_GEN(dev_priv) > 6) { i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); u32 val; @@ -5274,7 +5274,7 @@ void intel_edp_drrs_flush(struct drm_device *dev, INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); mutex_init(&dev_priv->drrs.mutex); - if (INTEL_INFO(dev)->gen <= 6) { + if (INTEL_GEN(dev_priv) <= 6) { DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); return NULL; } @@ -5429,7 +5429,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, intel_dp->pps_pipe = INVALID_PIPE; /* intel_dp vfuncs */ - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -5438,7 +5438,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -5615,7 +5615,7 @@ bool intel_dp_init(struct drm_device *dev, } else { intel_encoder->pre_enable = g4x_pre_enable_dp; intel_encoder->enable = g4x_enable_dp; - if (INTEL_INFO(dev)->gen >= 5) + if (INTEL_GEN(dev_priv) >= 5) intel_encoder->post_disable = ilk_post_disable_dp; } diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index c0eff15..fce4052 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -156,7 +156,7 @@ void intel_disable_shared_dpll(struct intel_crtc *crtc) unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base); /* PCH only available on ILK+ */ - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) return; if (pll == NULL) diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 62eaa89..ae19a62 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -122,12 +122,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) pipe_config->gmch_pfit.lvds_border_bits = tmp & LVDS_BORDER_ENABLE; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_INFO(dev)->gen < 4) { + if (INTEL_GEN(dev_priv) < 4) { tmp = I915_READ(PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 658a756..6e0a6d9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2155,14 +2155,14 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) wm[2] = (sskpd >> 12) & 0xFF; wm[3] = (sskpd >> 20) & 0x1FF; wm[4] = (sskpd >> 32) & 0x1FF; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (INTEL_GEN(dev_priv) >= 6) { uint32_t sskpd = I915_READ(MCH_SSKPD); wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; - } else if (INTEL_INFO(dev)->gen >= 5) { + } else if (INTEL_GEN(dev_priv) >= 5) { uint32_t mltr = I915_READ(MLTR_ILK); /* ILK primary LP0 latency is 700 ns */ @@ -2367,7 +2367,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) usable_level = max_level; /* ILK/SNB: LP2+ watermarks only w/o sprites */ - if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled) + if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) usable_level = 1; /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -2510,12 +2510,12 @@ static void ilk_wm_merge(struct drm_device *dev, int last_enabled_level = max_level; /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ - if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && + if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev)) && config->num_pipes_active > 1) last_enabled_level = 0; /* ILK: FBC WM must be disabled always */ - merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; + merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { @@ -2821,7 +2821,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, previous->wm_lp_spr[0] != results->wm_lp_spr[0]) I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) @@ -4056,7 +4056,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); /* 5/6 split only in single pipe config on IVB+ */ - if (INTEL_INFO(dev)->gen >= 7 && + if (INTEL_GEN(dev_priv) >= 7 && config.num_pipes_active == 1 && config.sprites_enabled) { ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); @@ -4435,7 +4435,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) hw->wm_lp[2] = I915_READ(WM3_LP_ILK); hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); - if (INTEL_INFO(dev)->gen >= 7) { + if (INTEL_GEN(dev_priv) >= 7) { hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); } @@ -7537,7 +7537,7 @@ void intel_init_pm(struct drm_device *dev) i915_ironlake_get_mem_freq(dev); /* For FIFO watermark updates */ - if (INTEL_INFO(dev)->gen >= 9) { + if (INTEL_GEN(dev_priv) >= 9) { skl_setup_wm_latency(dev); dev_priv->display.update_wm = skl_update_wm; dev_priv->display.compute_global_watermarks = skl_compute_wm; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 29a09bf..3d9b67a 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -455,7 +455,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) /* Enable PSR on the panel */ hsw_psr_enable_sink(intel_dp); - if (INTEL_INFO(dev)->gen >= 9) + if (INTEL_GEN(dev_priv) >= 9) intel_psr_activate(intel_dp); } else { vlv_psr_setup_vsc(intel_dp); @@ -481,7 +481,7 @@ void intel_psr_enable(struct intel_dp *intel_dp) * - On HSW/BDW we get a recoverable frozen screen until next * exit-activate sequence. */ - if (INTEL_INFO(dev)->gen < 9) + if (INTEL_GEN(dev_priv) < 9) schedule_delayed_work(&dev_priv->psr.work, msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 1a71456..f4e1b74 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1271,13 +1271,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) return; /* Set the SDVO control regs. */ - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; - if (INTEL_INFO(dev)->gen < 5) + if (INTEL_GEN(dev_priv) < 5) sdvox |= SDVO_BORDER_ENABLE; } else { sdvox = I915_READ(intel_sdvo->sdvo_reg); @@ -1296,7 +1296,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) if (intel_sdvo->has_hdmi_audio) sdvox |= SDVO_AUDIO_ENABLE; - if (INTEL_INFO(dev)->gen >= 4) { + if (INTEL_GEN(dev_priv) >= 4) { /* done in crtc_mode_set as the dpll_md reg must be written early */ } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { /* done in crtc_mode_set as it lives inside the dpll register */ @@ -1306,7 +1306,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - INTEL_INFO(dev)->gen < 5) + INTEL_GEN(dev_priv) < 5) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 1f3a0e1..71a65ef 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1099,7 +1099,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder) set_color_conversion(dev_priv, color_conversion); - if (INTEL_INFO(dev)->gen >= 4) + if (INTEL_GEN(dev_priv) >= 4) I915_WRITE(TV_CLR_KNOBS, 0x00404000); else I915_WRITE(TV_CLR_KNOBS, 0x00606000);
More Coccinellery ... Wherever we find "INTEL_INFO(dev)->gen", and have a suitable "dev_priv" in scope, replace it with "INTEL_GEN(dev_priv)". At this time, we've found 189 instances, and each replacement saves one memory cycle at runtime and two bytes of codespace (~360 bytes total text size reduction). @dev_priv_param@ function FUNC; idexpression struct drm_device *DEV; identifier DEV_PRIV; @@ FUNC(..., struct drm_i915_private *DEV_PRIV, ...) { <... - INTEL_INFO(DEV)->gen + INTEL_GEN(DEV_PRIV) ...> } @dev_priv_local@ idexpression struct drm_device *DEV; identifier DEV_PRIV; expression E; @@ { ... ( struct drm_i915_private *DEV_PRIV; | struct drm_i915_private *DEV_PRIV = E; ) <... - INTEL_INFO(DEV)->gen + INTEL_GEN(DEV_PRIV) ...> } Plus manual deletion of one now-unused local "dev". Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 52 +++++++------- drivers/gpu/drm/i915/i915_dma.c | 16 ++--- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 4 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-- drivers/gpu/drm/i915/i915_gem_fence.c | 8 +-- drivers/gpu/drm/i915/i915_gem_gtt.c | 12 ++-- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 14 ++-- drivers/gpu/drm/i915/i915_irq.c | 12 ++-- drivers/gpu/drm/i915/i915_suspend.c | 20 +++--- drivers/gpu/drm/i915/intel_color.c | 2 +- drivers/gpu/drm/i915/intel_crt.c | 6 +- drivers/gpu/drm/i915/intel_ddi.c | 4 +- drivers/gpu/drm/i915/intel_display.c | 111 ++++++++++++++--------------- drivers/gpu/drm/i915/intel_dp.c | 20 +++--- drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_pm.c | 18 ++--- drivers/gpu/drm/i915/intel_psr.c | 4 +- drivers/gpu/drm/i915/intel_sdvo.c | 8 +-- drivers/gpu/drm/i915/intel_tv.c | 2 +- 22 files changed, 167 insertions(+), 168 deletions(-)