From patchwork Fri Jun 17 07:09:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 9182697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 696826075F for ; Fri, 17 Jun 2016 07:09:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 580F41FF21 for ; Fri, 17 Jun 2016 07:09:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4D2A828399; Fri, 17 Jun 2016 07:09:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 187661FF21 for ; Fri, 17 Jun 2016 07:09:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A61FC6E1B1; Fri, 17 Jun 2016 07:09:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 98EE26E1B1 for ; Fri, 17 Jun 2016 07:09:24 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 17 Jun 2016 00:09:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.26,482,1459839600"; d="scan'208"; a="1003894712" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by fmsmga002.fm.intel.com with ESMTP; 17 Jun 2016 00:09:23 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Jun 2016 08:09:02 +0100 Message-Id: <1466147355-4635-3-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466147355-4635-1-git-send-email-arun.siluvery@linux.intel.com> References: <1466147355-4635-1-git-send-email-arun.siluvery@linux.intel.com> Subject: [Intel-gfx] [PATCH v2 02/15] drm/i915/tdr: Extend the idea of reset_counter to engine reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This change extends the idea of reset_counter variable to engine reset by creating additional variables for each engine. Least significant bit is set to mark the engine reset is pending and once reset is successful it is incremented again, this is further used to count the no of engine resets. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_drv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9fa9698..8bb05b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1401,6 +1401,12 @@ struct i915_gpu_error { #define I915_RESET_IN_PROGRESS_FLAG 1 #define I915_WEDGED (1 << 31) + /* indicates request to reset engine */ +#define I915_ENGINE_RESET_IN_PROGRESS (1<<0) + + /* extending the idea of reset_counter to engine reset */ + atomic_t engine_reset_counter[I915_NUM_ENGINES]; + /** * Waitqueue to signal when the reset has completed. Used by clients * that wait for dev_priv->mm.wedged to settle. @@ -3296,6 +3302,19 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error) return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2; } +static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error, + u32 engine_id) +{ + return unlikely(atomic_read(&error->engine_reset_counter[engine_id]) + & I915_ENGINE_RESET_IN_PROGRESS); +} + +static inline u32 i915_engine_reset_count(struct i915_gpu_error *error, + struct intel_engine_cs *engine) +{ + return (atomic_read(&error->engine_reset_counter[engine->id]) + 1) / 2; +} + static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) { return dev_priv->gpu_error.stop_rings == 0 ||