From patchwork Tue Jun 21 18:11:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Antoine X-Patchwork-Id: 9191203 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A93526089F for ; Tue, 21 Jun 2016 18:14:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9CECB28169 for ; Tue, 21 Jun 2016 18:14:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 918A02832C; Tue, 21 Jun 2016 18:14:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C17328319 for ; Tue, 21 Jun 2016 18:14:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19F036E2C7; Tue, 21 Jun 2016 18:14:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 186216E2BE for ; Tue, 21 Jun 2016 18:14:42 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 21 Jun 2016 11:11:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,505,1459839600"; d="scan'208";a="992330443" Received: from peterant-linux2.isw.intel.com ([10.102.226.53]) by fmsmga001.fm.intel.com with ESMTP; 21 Jun 2016 11:11:48 -0700 From: Peter Antoine To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2016 19:11:25 +0100 Message-Id: <1466532685-5101-7-git-send-email-peter.antoine@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466532685-5101-1-git-send-email-peter.antoine@intel.com> References: <1466532685-5101-1-git-send-email-peter.antoine@intel.com> Cc: sean.v.kelley@intel.com, lawrence.t.li@intel.com, rodrigo.vivi@intel.com Subject: [Intel-gfx] [PATCH 6/6] drm/i915/huc: Add BXT HuC Loading Support X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the HuC Loading for the BXT. Version 1.x of the HuC firmware. Signed-off-by: Peter Antoine --- drivers/gpu/drm/i915/i915_gem.c | 13 +++---------- drivers/gpu/drm/i915/intel_guc_loader.c | 29 +++++++++++++++++------------ drivers/gpu/drm/i915/intel_huc_loader.c | 7 +++++++ 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 549dd3f..6abd5e5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5143,16 +5143,9 @@ i915_gem_init_hw(struct drm_device *dev) intel_mocs_init_l3cc_table(dev); /* We can't enable contexts until all firmware is loaded */ - if (HAS_GUC(dev)) { - /* init WOPCM */ - I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev)); - I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); - - intel_huc_load(dev); - ret = intel_guc_setup(dev); - if (ret) - goto out; - } + ret = intel_guc_setup(dev); + if (ret) + goto out; /* * Increment the next seqno by 0x100 so we have a visible break diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index e876a23f..289b5b6 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -82,6 +82,17 @@ const char *intel_uc_fw_status_repr(enum intel_uc_fw_status status) } }; +u32 guc_wopcm_size(struct drm_device *dev) +{ + u32 wopcm_size = GUC_WOPCM_TOP; + + /* On BXT, the top of WOPCM is reserved for RC6 context */ + if (IS_BROXTON(dev)) + wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED; + + return wopcm_size; +} + static void direct_interrupts_to_host(struct drm_i915_private *dev_priv) { struct intel_engine_cs *engine; @@ -296,17 +307,6 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv) return ret; } -u32 guc_wopcm_size(struct drm_device *dev) -{ - u32 wopcm_size = GUC_WOPCM_TOP; - - /* On BXT, the top of WOPCM is reserved for RC6 context */ - if (IS_BROXTON(dev)) - wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED; - - return wopcm_size; -} - /* * Load the GuC firmware blob into the MinuteIA. */ @@ -333,6 +333,10 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + /* init WOPCM */ + I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev)); + I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE); + /* Enable MIA caching. GuC clock gating is disabled. */ I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE); @@ -483,6 +487,7 @@ int intel_guc_setup(struct drm_device *dev) goto fail; } + intel_huc_load(dev); err = guc_ucode_xfer(dev_priv); if (!err) break; @@ -638,7 +643,7 @@ void intel_uc_fw_fetch(struct drm_device *dev, struct intel_uc_fw *uc_fw) size = uc_fw->header_size + uc_fw->ucode_size; /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ - if (size > guc_wopcm_size(dev->dev_private)) { + if (size > guc_wopcm_size(dev)) { DRM_ERROR("Firmware is too large to fit in WOPCM\n"); goto fail; } diff --git a/drivers/gpu/drm/i915/intel_huc_loader.c b/drivers/gpu/drm/i915/intel_huc_loader.c index 7205e9e..7a43d4e 100644 --- a/drivers/gpu/drm/i915/intel_huc_loader.c +++ b/drivers/gpu/drm/i915/intel_huc_loader.c @@ -49,6 +49,9 @@ #define I915_SKL_HUC_UCODE "i915/skl_huc_ver1.bin" MODULE_FIRMWARE(I915_SKL_HUC_UCODE); +#define I915_BXT_HUC_UCODE "i915/bxt_huc_ver1.bin" +MODULE_FIRMWARE(I915_BXT_HUC_UCODE); + /** * intel_huc_load_ucode() - DMA's the firmware * @dev: the drm device @@ -157,6 +160,10 @@ void intel_huc_init(struct drm_device *dev) fw_path = I915_SKL_HUC_UCODE; huc_fw->major_ver_wanted = 1; huc_fw->minor_ver_wanted = 5; + } else if (IS_BROXTON(dev)) { + fw_path = I915_BXT_HUC_UCODE; + huc_fw->major_ver_wanted = 1; + huc_fw->minor_ver_wanted = 0; } if (fw_path == NULL)