| Message ID | 1467301589-21541-1-git-send-email-david.s.gordon@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 30/06/16 16:46, Dave Gordon wrote: > intel_lrc.c has a table of "logical rings" (meaning engines), while > intel_ringbuffer.c has separately open-coded initialisation for each > engine. We can deduplicate this somewhat by using the same first-stage > engine-setup function for both modes. > > So here we expose the function that transfers information from the > static table of (all) known engines to the dev_priv->engine array of > engines available on this device (adjusting the names along the way) > and then embed calls to it in both the LRC and the legacy-mode setup. > > Signed-off-by: Dave Gordon <david.s.gordon@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 40 +++++++++++++++++++++------------ > drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++----------------------- > drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++ > 3 files changed, 41 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 62b0dc6..bd6266e 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1991,8 +1991,9 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine) > } > > static inline void > -logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) > +logical_ring_default_irqs(struct intel_engine_cs *engine) > { > + unsigned shift = engine->irq_shift; > engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; > engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; > init_waitqueue_head(&engine->irq_queue); > @@ -2093,14 +2094,14 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) > return ret; > } > > -static const struct logical_ring_info { > +static const struct engine_info { > const char *name; > unsigned exec_id; > unsigned guc_id; > u32 mmio_base; > unsigned irq_shift; > int (*init)(struct intel_engine_cs *engine); > -} logical_rings[] = { > +} intel_engines[] = { > [RCS] = { > .name = "render ring", > .exec_id = I915_EXEC_RENDER, > @@ -2143,20 +2144,31 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) > }, > }; > > -static struct intel_engine_cs * > -logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id) > +struct intel_engine_cs * > +intel_engine_setup(struct drm_i915_private *dev_priv, > + enum intel_engine_id id) > { > - const struct logical_ring_info *info = &logical_rings[id]; > + const struct engine_info *info = &intel_engines[id]; > struct intel_engine_cs *engine = &dev_priv->engine[id]; > - enum forcewake_domains fw_domains; > > engine->id = id; > + engine->i915 = dev_priv; > engine->name = info->name; > engine->exec_id = info->exec_id; > - engine->guc_id = info->guc_id; > + engine->hw_id = engine->guc_id = info->guc_id; > engine->mmio_base = info->mmio_base; > + engine->irq_shift = info->irq_shift; > > - engine->i915 = dev_priv; > + return engine; > +} > + > +static struct intel_engine_cs * > +logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id) > +{ > + struct intel_engine_cs *engine; > + enum forcewake_domains fw_domains; > + > + engine = intel_engine_setup(dev_priv, id); > > /* Intentionally left blank. */ > engine->buffer = NULL; > @@ -2186,7 +2198,7 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) > > logical_ring_init_platform_invariants(engine); > logical_ring_default_vfuncs(engine); > - logical_ring_default_irqs(engine, info->irq_shift); > + logical_ring_default_irqs(engine); > > intel_engine_init_hangcheck(engine); > i915_gem_batch_pool_init(dev_priv->dev, &engine->batch_pool); > @@ -2215,14 +2227,14 @@ int intel_logical_rings_init(struct drm_device *dev) > WARN_ON(INTEL_INFO(dev_priv)->ring_mask & > GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); > > - for (i = 0; i < ARRAY_SIZE(logical_rings); i++) { > + for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { > if (!HAS_ENGINE(dev_priv, i)) > continue; > > - if (!logical_rings[i].init) > + if (!intel_engines[i].init) > continue; > > - ret = logical_rings[i].init(logical_ring_setup(dev_priv, i)); > + ret = intel_engines[i].init(logical_ring_setup(dev_priv, i)); > if (ret) > goto cleanup; > > @@ -2230,7 +2242,7 @@ int intel_logical_rings_init(struct drm_device *dev) > } > > /* > - * Catch failures to update logical_rings table when the new engines > + * Catch failures to update intel_engines table when the new engines > * are added to the driver by a warning and disabling the forgotten > * engines. > */ > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 04a2d14..e6020a4 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -2876,15 +2876,11 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, > int intel_init_render_ring_buffer(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_engine_cs *engine = &dev_priv->engine[RCS]; > + struct intel_engine_cs *engine; > struct drm_i915_gem_object *obj; > int ret; > > - engine->name = "render ring"; > - engine->id = RCS; > - engine->exec_id = I915_EXEC_RENDER; > - engine->hw_id = 0; > - engine->mmio_base = RENDER_RING_BASE; > + engine = intel_engine_setup(dev_priv, RCS); > > if (INTEL_GEN(dev_priv) >= 8) { > if (i915_semaphore_is_enabled(dev_priv)) { > @@ -3029,12 +3025,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > int intel_init_bsd_ring_buffer(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_engine_cs *engine = &dev_priv->engine[VCS]; > + struct intel_engine_cs *engine; > > - engine->name = "bsd ring"; > - engine->id = VCS; > - engine->exec_id = I915_EXEC_BSD; > - engine->hw_id = 1; > + engine = intel_engine_setup(dev_priv, VCS); > > engine->write_tail = ring_write_tail; > if (INTEL_GEN(dev_priv) >= 6) { > @@ -3108,15 +3101,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > int intel_init_bsd2_ring_buffer(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; > + struct intel_engine_cs *engine; > > - engine->name = "bsd2 ring"; > - engine->id = VCS2; > - engine->exec_id = I915_EXEC_BSD; > - engine->hw_id = 4; > + engine = intel_engine_setup(dev_priv, VCS2); > > engine->write_tail = ring_write_tail; > - engine->mmio_base = GEN8_BSD2_RING_BASE; > engine->flush = gen6_bsd_ring_flush; > engine->add_request = gen6_add_request; > engine->irq_seqno_barrier = gen6_seqno_barrier; > @@ -3141,14 +3130,10 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) > int intel_init_blt_ring_buffer(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_engine_cs *engine = &dev_priv->engine[BCS]; > + struct intel_engine_cs *engine; > > - engine->name = "blitter ring"; > - engine->id = BCS; > - engine->exec_id = I915_EXEC_BLT; > - engine->hw_id = 2; > + engine = intel_engine_setup(dev_priv, BCS); > > - engine->mmio_base = BLT_RING_BASE; > engine->write_tail = ring_write_tail; > engine->flush = gen6_ring_flush; > engine->add_request = gen6_add_request; > @@ -3201,14 +3186,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) > int intel_init_vebox_ring_buffer(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - struct intel_engine_cs *engine = &dev_priv->engine[VECS]; > + struct intel_engine_cs *engine; > > - engine->name = "video enhancement ring"; > - engine->id = VECS; > - engine->exec_id = I915_EXEC_VEBOX; > - engine->hw_id = 3; > + engine = intel_engine_setup(dev_priv, VECS); > > - engine->mmio_base = VEBOX_RING_BASE; > engine->write_tail = ring_write_tail; > engine->flush = gen6_ring_flush; > engine->add_request = gen6_add_request; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index b33c876..c512e43 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -157,6 +157,7 @@ struct intel_engine_cs { > unsigned int hw_id; > unsigned int guc_id; /* XXX same as hw_id? */ > u32 mmio_base; > + unsigned int irq_shift; > struct intel_ringbuffer *buffer; > struct list_head buffers; > > @@ -347,6 +348,10 @@ struct intel_engine_cs { > u32 (*get_cmd_length_mask)(u32 cmd_header); > }; > > +struct intel_engine_cs * > +intel_engine_setup(struct drm_i915_private *dev_priv, > + enum intel_engine_id id); > + > static inline bool > intel_engine_initialized(struct intel_engine_cs *engine) > { > It won't apply any more due my patches but an ack from me. After this one we can progress towards an unified engine init / teardown with a little bit additional re-shuffling I think. Maybe have two constructors in the engine_info array (one for ringbuff and one for execlists) and a common intel_engine_setup. Or something like that. Regards, Tvrtko
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 62b0dc6..bd6266e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1991,8 +1991,9 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine) } static inline void -logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift) +logical_ring_default_irqs(struct intel_engine_cs *engine) { + unsigned shift = engine->irq_shift; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; init_waitqueue_head(&engine->irq_queue); @@ -2093,14 +2094,14 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) return ret; } -static const struct logical_ring_info { +static const struct engine_info { const char *name; unsigned exec_id; unsigned guc_id; u32 mmio_base; unsigned irq_shift; int (*init)(struct intel_engine_cs *engine); -} logical_rings[] = { +} intel_engines[] = { [RCS] = { .name = "render ring", .exec_id = I915_EXEC_RENDER, @@ -2143,20 +2144,31 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) }, }; -static struct intel_engine_cs * -logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id) +struct intel_engine_cs * +intel_engine_setup(struct drm_i915_private *dev_priv, + enum intel_engine_id id) { - const struct logical_ring_info *info = &logical_rings[id]; + const struct engine_info *info = &intel_engines[id]; struct intel_engine_cs *engine = &dev_priv->engine[id]; - enum forcewake_domains fw_domains; engine->id = id; + engine->i915 = dev_priv; engine->name = info->name; engine->exec_id = info->exec_id; - engine->guc_id = info->guc_id; + engine->hw_id = engine->guc_id = info->guc_id; engine->mmio_base = info->mmio_base; + engine->irq_shift = info->irq_shift; - engine->i915 = dev_priv; + return engine; +} + +static struct intel_engine_cs * +logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id) +{ + struct intel_engine_cs *engine; + enum forcewake_domains fw_domains; + + engine = intel_engine_setup(dev_priv, id); /* Intentionally left blank. */ engine->buffer = NULL; @@ -2186,7 +2198,7 @@ static int logical_render_ring_init(struct intel_engine_cs *engine) logical_ring_init_platform_invariants(engine); logical_ring_default_vfuncs(engine); - logical_ring_default_irqs(engine, info->irq_shift); + logical_ring_default_irqs(engine); intel_engine_init_hangcheck(engine); i915_gem_batch_pool_init(dev_priv->dev, &engine->batch_pool); @@ -2215,14 +2227,14 @@ int intel_logical_rings_init(struct drm_device *dev) WARN_ON(INTEL_INFO(dev_priv)->ring_mask & GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); - for (i = 0; i < ARRAY_SIZE(logical_rings); i++) { + for (i = 0; i < ARRAY_SIZE(intel_engines); i++) { if (!HAS_ENGINE(dev_priv, i)) continue; - if (!logical_rings[i].init) + if (!intel_engines[i].init) continue; - ret = logical_rings[i].init(logical_ring_setup(dev_priv, i)); + ret = intel_engines[i].init(logical_ring_setup(dev_priv, i)); if (ret) goto cleanup; @@ -2230,7 +2242,7 @@ int intel_logical_rings_init(struct drm_device *dev) } /* - * Catch failures to update logical_rings table when the new engines + * Catch failures to update intel_engines table when the new engines * are added to the driver by a warning and disabling the forgotten * engines. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 04a2d14..e6020a4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2876,15 +2876,11 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req, int intel_init_render_ring_buffer(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *engine = &dev_priv->engine[RCS]; + struct intel_engine_cs *engine; struct drm_i915_gem_object *obj; int ret; - engine->name = "render ring"; - engine->id = RCS; - engine->exec_id = I915_EXEC_RENDER; - engine->hw_id = 0; - engine->mmio_base = RENDER_RING_BASE; + engine = intel_engine_setup(dev_priv, RCS); if (INTEL_GEN(dev_priv) >= 8) { if (i915_semaphore_is_enabled(dev_priv)) { @@ -3029,12 +3025,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev) int intel_init_bsd_ring_buffer(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *engine = &dev_priv->engine[VCS]; + struct intel_engine_cs *engine; - engine->name = "bsd ring"; - engine->id = VCS; - engine->exec_id = I915_EXEC_BSD; - engine->hw_id = 1; + engine = intel_engine_setup(dev_priv, VCS); engine->write_tail = ring_write_tail; if (INTEL_GEN(dev_priv) >= 6) { @@ -3108,15 +3101,11 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) int intel_init_bsd2_ring_buffer(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *engine = &dev_priv->engine[VCS2]; + struct intel_engine_cs *engine; - engine->name = "bsd2 ring"; - engine->id = VCS2; - engine->exec_id = I915_EXEC_BSD; - engine->hw_id = 4; + engine = intel_engine_setup(dev_priv, VCS2); engine->write_tail = ring_write_tail; - engine->mmio_base = GEN8_BSD2_RING_BASE; engine->flush = gen6_bsd_ring_flush; engine->add_request = gen6_add_request; engine->irq_seqno_barrier = gen6_seqno_barrier; @@ -3141,14 +3130,10 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) int intel_init_blt_ring_buffer(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *engine = &dev_priv->engine[BCS]; + struct intel_engine_cs *engine; - engine->name = "blitter ring"; - engine->id = BCS; - engine->exec_id = I915_EXEC_BLT; - engine->hw_id = 2; + engine = intel_engine_setup(dev_priv, BCS); - engine->mmio_base = BLT_RING_BASE; engine->write_tail = ring_write_tail; engine->flush = gen6_ring_flush; engine->add_request = gen6_add_request; @@ -3201,14 +3186,10 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) int intel_init_vebox_ring_buffer(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - struct intel_engine_cs *engine = &dev_priv->engine[VECS]; + struct intel_engine_cs *engine; - engine->name = "video enhancement ring"; - engine->id = VECS; - engine->exec_id = I915_EXEC_VEBOX; - engine->hw_id = 3; + engine = intel_engine_setup(dev_priv, VECS); - engine->mmio_base = VEBOX_RING_BASE; engine->write_tail = ring_write_tail; engine->flush = gen6_ring_flush; engine->add_request = gen6_add_request; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index b33c876..c512e43 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -157,6 +157,7 @@ struct intel_engine_cs { unsigned int hw_id; unsigned int guc_id; /* XXX same as hw_id? */ u32 mmio_base; + unsigned int irq_shift; struct intel_ringbuffer *buffer; struct list_head buffers; @@ -347,6 +348,10 @@ struct intel_engine_cs { u32 (*get_cmd_length_mask)(u32 cmd_header); }; +struct intel_engine_cs * +intel_engine_setup(struct drm_i915_private *dev_priv, + enum intel_engine_id id); + static inline bool intel_engine_initialized(struct intel_engine_cs *engine) {
intel_lrc.c has a table of "logical rings" (meaning engines), while intel_ringbuffer.c has separately open-coded initialisation for each engine. We can deduplicate this somewhat by using the same first-stage engine-setup function for both modes. So here we expose the function that transfers information from the static table of (all) known engines to the dev_priv->engine array of engines available on this device (adjusting the names along the way) and then embed calls to it in both the LRC and the legacy-mode setup. Signed-off-by: Dave Gordon <david.s.gordon@intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 40 +++++++++++++++++++++------------ drivers/gpu/drm/i915/intel_ringbuffer.c | 39 +++++++++----------------------- drivers/gpu/drm/i915/intel_ringbuffer.h | 5 +++++ 3 files changed, 41 insertions(+), 43 deletions(-)