From patchwork Wed Jul 13 13:01:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gordon X-Patchwork-Id: 9227547 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 221CA6086B for ; Wed, 13 Jul 2016 13:01:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 101492522B for ; Wed, 13 Jul 2016 13:01:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00B50271FD; Wed, 13 Jul 2016 13:01:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E04952522B for ; Wed, 13 Jul 2016 13:01:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BC3E6E728; Wed, 13 Jul 2016 13:01:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 592126E728 for ; Wed, 13 Jul 2016 13:01:31 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 13 Jul 2016 06:01:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,357,1464678000"; d="scan'208";a="994385166" Received: from dsgordon-linux2.isw.intel.com ([10.102.226.88]) by orsmga001.jf.intel.com with ESMTP; 13 Jul 2016 06:01:14 -0700 From: Dave Gordon To: intel-gfx@lists.freedesktop.org Date: Wed, 13 Jul 2016 14:01:11 +0100 Message-Id: <1468414871-25460-1-git-send-email-david.s.gordon@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <577BA8D4.4050602@intel.com> References: <577BA8D4.4050602@intel.com> Organization: Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ Subject: [Intel-gfx] [PATCH] drm/i915/guc: symbolic names for user load/submission preferences X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The existing code that accesses the "enable_guc_loading" and "enable_guc_submission" parameters uses explicit numerical values for the various possibilities, including in some cases relying on boolean 0/1 mapping to specific values (which could be confusing for maintainers). So this patch just provides and uses names for the values representing the DEFAULT, DISABLED, PREFERRED, and MANDATORY options that the user can select (-1, 0, 1, 2 respectively). This should produce identical code to the previous version! Signed-off-by: Dave Gordon Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- drivers/gpu/drm/i915/intel_guc.h | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_guc_loader.c | 26 ++++++++++++++------------ drivers/gpu/drm/i915/intel_lrc.c | 6 +++--- 4 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 2112e02..33c0e0ab 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -971,7 +971,7 @@ int i915_guc_submission_init(struct drm_i915_private *dev_priv) bitmap_clear(guc->doorbell_bitmap, 0, GUC_MAX_DOORBELLS); i915_guc_submission_disable(dev_priv); - if (!i915.enable_guc_submission) + if (i915.enable_guc_submission == GUC_SUBMISSION_DISABLED) return 0; /* not enabled */ if (guc->ctx_pool_obj) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 3e3e743..7ac835c 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -90,6 +90,21 @@ struct i915_guc_client { uint64_t submissions[I915_NUM_ENGINES]; }; +/* These represent user-requested preferences */ +enum { + GUC_SUBMISSION_DEFAULT = -1, + GUC_SUBMISSION_DISABLED = 0, + GUC_SUBMISSION_PREFERRED, + GUC_SUBMISSION_MANDATORY +}; +enum { + FIRMWARE_LOAD_DEFAULT = -1, + FIRMWARE_LOAD_DISABLED = 0, + FIRMWARE_LOAD_PREFERRED, + FIRMWARE_LOAD_MANDATORY +}; + +/* These represent the actual firmware status */ enum intel_guc_fw_status { GUC_FIRMWARE_FAIL = -1, GUC_FIRMWARE_NONE = 0, diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 605c696..2cd37db 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -189,7 +189,7 @@ static void set_guc_init_params(struct drm_i915_private *dev_priv) } /* If GuC submission is enabled, set up additional parameters here */ - if (i915.enable_guc_submission) { + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) { u32 pgs = i915_gem_obj_ggtt_offset(dev_priv->guc.ctx_pool_obj); u32 ctx_in_16 = GUC_MAX_GPU_CONTEXTS / 16; @@ -424,7 +424,7 @@ int intel_guc_setup(struct drm_device *dev) intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); /* Loading forbidden, or no firmware to load? */ - if (!i915.enable_guc_loading) { + if (i915.enable_guc_loading == FIRMWARE_LOAD_DISABLED) { err = 0; goto fail; } else if (fw_path == NULL) { @@ -493,7 +493,7 @@ int intel_guc_setup(struct drm_device *dev) intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status), intel_guc_fw_status_repr(guc_fw->guc_fw_load_status)); - if (i915.enable_guc_submission) { + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) { err = i915_guc_submission_enable(dev_priv); if (err) goto fail; @@ -519,9 +519,9 @@ int intel_guc_setup(struct drm_device *dev) * nonfatal error (i.e. it doesn't prevent driver load, but * marks the GPU as wedged until reset). */ - if (i915.enable_guc_loading > 1) { + if (i915.enable_guc_loading >= FIRMWARE_LOAD_MANDATORY) { ret = -EIO; - } else if (i915.enable_guc_submission > 1) { + } else if (i915.enable_guc_submission >= GUC_SUBMISSION_MANDATORY) { ret = -EIO; } else { ret = 0; @@ -536,7 +536,7 @@ int intel_guc_setup(struct drm_device *dev) else DRM_ERROR("GuC firmware load failed: %d\n", err); - if (i915.enable_guc_submission) { + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) { if (fw_path == NULL) DRM_INFO("GuC submission without firmware not supported\n"); if (ret == 0) @@ -544,7 +544,7 @@ int intel_guc_setup(struct drm_device *dev) else DRM_ERROR("GuC init failed: %d\n", ret); } - i915.enable_guc_submission = 0; + i915.enable_guc_submission = GUC_SUBMISSION_DISABLED; return ret; } @@ -686,10 +686,12 @@ void intel_guc_init(struct drm_device *dev) const char *fw_path; /* A negative value means "use platform default" */ - if (i915.enable_guc_loading < 0) - i915.enable_guc_loading = HAS_GUC_UCODE(dev); - if (i915.enable_guc_submission < 0) - i915.enable_guc_submission = HAS_GUC_SCHED(dev); + if (i915.enable_guc_loading <= FIRMWARE_LOAD_DEFAULT) + i915.enable_guc_loading = HAS_GUC_UCODE(dev) ? + FIRMWARE_LOAD_PREFERRED : FIRMWARE_LOAD_DISABLED; + if (i915.enable_guc_submission <= GUC_SUBMISSION_DEFAULT) + i915.enable_guc_submission = HAS_GUC_SCHED(dev) ? + GUC_SUBMISSION_PREFERRED : GUC_SUBMISSION_DISABLED; if (!HAS_GUC_UCODE(dev)) { fw_path = NULL; @@ -715,7 +717,7 @@ void intel_guc_init(struct drm_device *dev) guc_fw->guc_fw_load_status = GUC_FIRMWARE_NONE; /* Early (and silent) return if GuC loading is disabled */ - if (!i915.enable_guc_loading) + if (i915.enable_guc_loading == FIRMWARE_LOAD_DISABLED) return; if (fw_path == NULL) return; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 70c6990..2c530dc 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -719,7 +719,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request request->ringbuf = ce->ringbuf; - if (i915.enable_guc_submission) { + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) { /* * Check that the GuC has space for the request before * going any further, as the i915_add_request() call @@ -798,7 +798,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request request->previous_context = engine->last_context; engine->last_context = request->ctx; - if (i915.enable_guc_submission) + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) i915_guc_submit(request); else execlists_context_queue(request); @@ -992,7 +992,7 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx, ce->state->dirty = true; /* Invalidate GuC TLB. */ - if (i915.enable_guc_submission) + if (i915.enable_guc_submission != GUC_SUBMISSION_DISABLED) I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); return 0;