From patchwork Tue Jul 26 16:40:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: arun.siluvery@linux.intel.com X-Patchwork-Id: 9248437 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5597A607F2 for ; Tue, 26 Jul 2016 16:41:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4775726223 for ; Tue, 26 Jul 2016 16:41:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C50E271FD; Tue, 26 Jul 2016 16:41:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEE4126223 for ; Tue, 26 Jul 2016 16:41:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C912F6E559; Tue, 26 Jul 2016 16:41:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id D9B5D6E557 for ; Tue, 26 Jul 2016 16:41:30 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP; 26 Jul 2016 09:41:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,425,1464678000"; d="scan'208"; a="1014222516" Received: from asiluver-linux.isw.intel.com ([10.102.226.117]) by fmsmga001.fm.intel.com with ESMTP; 26 Jul 2016 09:41:10 -0700 From: Arun Siluvery To: intel-gfx@lists.freedesktop.org Date: Tue, 26 Jul 2016 17:40:49 +0100 Message-Id: <1469551257-26803-4-git-send-email-arun.siluvery@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1469551257-26803-1-git-send-email-arun.siluvery@linux.intel.com> References: <1469551257-26803-1-git-send-email-arun.siluvery@linux.intel.com> Subject: [Intel-gfx] [PATCH 03/11] drm/i915/tdr: Update reset_in_progress to account for engine reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now that we track reset progress using separate set of flags, update it to account for engine reset as well. A bit corresponding engine->id is set if reset is in progress for that engine. Bit0 is for full gpu reset. Signed-off-by: Arun Siluvery --- drivers/gpu/drm/i915/i915_drv.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 11436e7..125fafa 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1403,6 +1403,8 @@ struct i915_gpu_error { #define I915_RESET_IN_PROGRESS 0 #define I915_WEDGED (BITS_PER_LONG-1) + unsigned long engine_reset_count[I915_NUM_ENGINES]; + /** * Waitqueue to signal when a hang is detected. Used to for waiters * to release the struct_mutex for the reset to procede. @@ -3194,9 +3196,10 @@ i915_gem_find_active_request(struct intel_engine_cs *engine); void i915_gem_retire_requests(struct drm_i915_private *dev_priv); void i915_gem_retire_requests_ring(struct intel_engine_cs *engine); +/* indicates the progress of engine reset or full gpu reset */ static inline bool i915_reset_in_progress(struct i915_gpu_error *error) { - return test_bit(I915_RESET_IN_PROGRESS, &error->flags); + return unlikely(READ_ONCE(error->flags) & ~BIT(I915_WEDGED)); } static inline bool i915_terminally_wedged(struct i915_gpu_error *error) @@ -3214,6 +3217,17 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error) return READ_ONCE(error->reset_count); } +static inline bool i915_full_gpu_reset_in_progress(struct i915_gpu_error *error) +{ + return test_bit(I915_RESET_IN_PROGRESS, &error->flags); +} + +static inline bool i915_engine_reset_in_progress(struct i915_gpu_error *error, + struct intel_engine_cs *engine) +{ + return test_bit(engine->id + 1, &error->flags); +} + void i915_gem_reset(struct drm_device *dev); bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); int __must_check i915_gem_init(struct drm_device *dev);