@@ -776,6 +776,7 @@ struct intel_csr {
func(has_runtime_pm) sep \
func(has_core_ring_freq) sep \
func(has_csr) sep \
+ func(has_resource_streamer) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
func(cursor_needs_physical) sep \
@@ -2754,8 +2755,7 @@ struct drm_i915_cmd_table {
#define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
#define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
-#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
- INTEL_INFO(dev)->gen >= 8)
+#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->has_core_ring_freq)
@@ -265,7 +265,8 @@ static const struct intel_device_info intel_valleyview_d_info = {
.has_ddi = 1, \
.has_fpga_dbg = 1, \
.has_psr = 1, \
- .has_runtime_pm = 1
+ .has_runtime_pm = 1, \
+ .has_resource_streamer = 1
static const struct intel_device_info intel_haswell_d_info = {
HSW_FEATURES,
@@ -315,6 +316,7 @@ static const struct intel_device_info intel_cherryview_info = {
.is_cherryview = 1,
.has_psr = 1,
.has_runtime_pm = 1,
+ .has_resource_streamer = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -348,6 +350,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_runtime_pm = 1,
.has_pooled_eu = 0,
.has_csr = 1,
+ .has_resource_streamer = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,