| Message ID | 1470768327-14932-9-git-send-email-carlos.santa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Aug 09, 2016 at 11:45:14AM -0700, Carlos Santa wrote: > Moving all GPU features to the platform struct definition allows for > - standard place when adding new features from new platforms > - possible to see supported features when dumping struct > definitions > > Signed-off-by: Carlos Santa <carlos.santa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/i915_pci.c | 5 +++++ > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index e9d95c5..bc6df5b 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -774,6 +774,7 @@ struct intel_csr { > func(has_runtime_pm) sep \ > func(has_csr) sep \ > func(has_resource_streamer) sep \ > + func(has_rc6) sep \ > func(has_pipe_cxsr) sep \ > func(has_hotplug) sep \ > func(cursor_needs_physical) sep \ > @@ -2773,7 +2774,7 @@ struct drm_i915_cmd_table { > #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) > #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) > #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm) > -#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) > +#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) > #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) > > #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index 46c48ed..42108dc 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info = { > .has_fbc = 1, \ > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ > .has_llc = 1, \ > + .has_rc6 = 1, \ > GEN_DEFAULT_PIPEOFFSETS, \ > CURSOR_OFFSETS > > @@ -219,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { > .has_fbc = 1, \ > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ > .has_llc = 1, \ > + .has_rc6 = 1, \ > GEN_DEFAULT_PIPEOFFSETS, \ > IVB_CURSOR_OFFSETS > > @@ -243,6 +245,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { > .gen = 7, .num_pipes = 2, \ > .has_psr = 1, \ > .has_runtime_pm = 1, \ > + .has_rc6 = 1, \ > .need_gfx_hws = 1, .has_hotplug = 1, \ > .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ > .display_mmio_offset = VLV_DISPLAY_BASE, \ > @@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info = { > .has_psr = 1, > .has_runtime_pm = 1, > .has_resource_streamer = 1, > + .has_rc6 = 1, > .display_mmio_offset = VLV_DISPLAY_BASE, > GEN_CHV_PIPEOFFSETS, > CURSOR_OFFSETS, > @@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = { > .has_pooled_eu = 0, > .has_csr = 1, > .has_resource_streamer = 1, > + .has_rc6 = 1, > GEN_DEFAULT_PIPEOFFSETS, > IVB_CURSOR_OFFSETS, > BDW_COLORS, > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e9d95c5..bc6df5b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -774,6 +774,7 @@ struct intel_csr { func(has_runtime_pm) sep \ func(has_csr) sep \ func(has_resource_streamer) sep \ + func(has_rc6) sep \ func(has_pipe_cxsr) sep \ func(has_hotplug) sep \ func(cursor_needs_physical) sep \ @@ -2773,7 +2774,7 @@ struct drm_i915_cmd_table { #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr) #define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm) -#define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) +#define HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) #define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 46c48ed..42108dc 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -201,6 +201,7 @@ static const struct intel_device_info intel_ironlake_m_info = { .has_fbc = 1, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .has_llc = 1, \ + .has_rc6 = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ CURSOR_OFFSETS @@ -219,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { .has_fbc = 1, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .has_llc = 1, \ + .has_rc6 = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ IVB_CURSOR_OFFSETS @@ -243,6 +245,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { .gen = 7, .num_pipes = 2, \ .has_psr = 1, \ .has_runtime_pm = 1, \ + .has_rc6 = 1, \ .need_gfx_hws = 1, .has_hotplug = 1, \ .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ .display_mmio_offset = VLV_DISPLAY_BASE, \ @@ -293,6 +296,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_psr = 1, .has_runtime_pm = 1, .has_resource_streamer = 1, + .has_rc6 = 1, .display_mmio_offset = VLV_DISPLAY_BASE, GEN_CHV_PIPEOFFSETS, CURSOR_OFFSETS, @@ -327,6 +331,7 @@ static const struct intel_device_info intel_broxton_info = { .has_pooled_eu = 0, .has_csr = 1, .has_resource_streamer = 1, + .has_rc6 = 1, GEN_DEFAULT_PIPEOFFSETS, IVB_CURSOR_OFFSETS, BDW_COLORS,
Moving all GPU features to the platform struct definition allows for - standard place when adding new features from new platforms - possible to see supported features when dumping struct definitions Signed-off-by: Carlos Santa <carlos.santa@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/i915_pci.c | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-)