| Message ID | 1470770955-5214-9-git-send-email-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > Of Manasi Navare > Sent: Wednesday, August 10, 2016 12:59 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Split hsw_get_dpll() > > Split out the DisplayPort and HDMI pll setup code into separate > functions and refactor the DP code that calculates the pll > so that it doesn't depend on crtc state. > This will be used for acquiring port pll when doing > upfront link training. > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Thanks, Durga > --- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 90 ++++++++++++++++++++++---- > --------- > drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 +++ > 2 files changed, 63 insertions(+), 33 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index e5c025e..93f7aae 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -705,11 +705,65 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, > *r2_out = best.r2; > } > > +static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock, > + struct intel_crtc *crtc, > + struct intel_crtc_state > *crtc_state) > +{ > + struct intel_shared_dpll *pll; > + uint32_t val; > + unsigned p, n2, r2; > + > + hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); > + > + val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | > + WRPLL_DIVIDER_REFERENCE(r2) | > WRPLL_DIVIDER_FEEDBACK(n2) | > + WRPLL_DIVIDER_POST(p); > + > + crtc_state->dpll_hw_state.wrpll = val; > + > + pll = intel_find_shared_dpll(crtc, crtc_state, > + DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); > + > + if (!pll) > + return NULL; > + > + return pll; > +} > + > +struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder > *encoder, > + int clock) > +{ > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + struct intel_shared_dpll *pll; > + enum intel_dpll_id pll_id; > + > + switch (clock / 2) { > + case 81000: > + pll_id = DPLL_ID_LCPLL_810; > + break; > + case 135000: > + pll_id = DPLL_ID_LCPLL_1350; > + break; > + case 270000: > + pll_id = DPLL_ID_LCPLL_2700; > + break; > + default: > + DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); > + return NULL; > + } > + > + pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); > + > + if (!pll) > + return NULL; > + > + return pll; > +} > + > static struct intel_shared_dpll * > hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, > struct intel_encoder *encoder) > { > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_shared_dpll *pll; > int clock = crtc_state->port_clock; > > @@ -717,41 +771,12 @@ hsw_get_dpll(struct intel_crtc *crtc, struct > intel_crtc_state *crtc_state, > sizeof(crtc_state->dpll_hw_state)); > > if (encoder->type == INTEL_OUTPUT_HDMI) { > - uint32_t val; > - unsigned p, n2, r2; > - > - hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); > - > - val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | > - WRPLL_DIVIDER_REFERENCE(r2) | > WRPLL_DIVIDER_FEEDBACK(n2) | > - WRPLL_DIVIDER_POST(p); > - > - crtc_state->dpll_hw_state.wrpll = val; > - > - pll = intel_find_shared_dpll(crtc, crtc_state, > - DPLL_ID_WRPLL1, > DPLL_ID_WRPLL2); > + pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state); > > } else if (encoder->type == INTEL_OUTPUT_DP || > encoder->type == INTEL_OUTPUT_DP_MST || > encoder->type == INTEL_OUTPUT_EDP) { > - enum intel_dpll_id pll_id; > - > - switch (clock / 2) { > - case 81000: > - pll_id = DPLL_ID_LCPLL_810; > - break; > - case 135000: > - pll_id = DPLL_ID_LCPLL_1350; > - break; > - case 270000: > - pll_id = DPLL_ID_LCPLL_2700; > - break; > - default: > - DRM_DEBUG_KMS("Invalid clock for DP: %d\n", > clock); > - return NULL; > - } > - > - pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); > + pll = hsw_ddi_dp_get_dpll(encoder, clock); > > } else if (encoder->type == INTEL_OUTPUT_ANALOG) { > if (WARN_ON(crtc_state->port_clock / 2 != 135000)) > @@ -774,7 +799,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct > intel_crtc_state *crtc_state, > return pll; > } > > - > static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { > .enable = hsw_ddi_wrpll_enable, > .disable = hsw_ddi_wrpll_disable, > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h > b/drivers/gpu/drm/i915/intel_dpll_mgr.h > index ec0fe66..f438535 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h > @@ -164,10 +164,16 @@ void intel_shared_dpll_init(struct drm_device > *dev); > bool bxt_ddi_dp_set_dpll_hw_state(int clock, > struct intel_dpll_hw_state *dpll_hw_state); > > + > /* SKL dpll related functions */ > bool skl_ddi_dp_set_dpll_hw_state(int clock, > struct intel_dpll_hw_state *dpll_hw_state); > struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private > *dev_priv, > int clock); > > + > +/* HSW dpll related functions */ > +struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder > *encoder, > + int clock); > + > #endif /* _INTEL_DPLL_MGR_H_ */ > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index e5c025e..93f7aae 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -705,11 +705,65 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, *r2_out = best.r2; } +static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock, + struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state) +{ + struct intel_shared_dpll *pll; + uint32_t val; + unsigned p, n2, r2; + + hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); + + val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | + WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | + WRPLL_DIVIDER_POST(p); + + crtc_state->dpll_hw_state.wrpll = val; + + pll = intel_find_shared_dpll(crtc, crtc_state, + DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); + + if (!pll) + return NULL; + + return pll; +} + +struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, + int clock) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_shared_dpll *pll; + enum intel_dpll_id pll_id; + + switch (clock / 2) { + case 81000: + pll_id = DPLL_ID_LCPLL_810; + break; + case 135000: + pll_id = DPLL_ID_LCPLL_1350; + break; + case 270000: + pll_id = DPLL_ID_LCPLL_2700; + break; + default: + DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); + return NULL; + } + + pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); + + if (!pll) + return NULL; + + return pll; +} + static struct intel_shared_dpll * hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; int clock = crtc_state->port_clock; @@ -717,41 +771,12 @@ hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, sizeof(crtc_state->dpll_hw_state)); if (encoder->type == INTEL_OUTPUT_HDMI) { - uint32_t val; - unsigned p, n2, r2; - - hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); - - val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | - WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | - WRPLL_DIVIDER_POST(p); - - crtc_state->dpll_hw_state.wrpll = val; - - pll = intel_find_shared_dpll(crtc, crtc_state, - DPLL_ID_WRPLL1, DPLL_ID_WRPLL2); + pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state); } else if (encoder->type == INTEL_OUTPUT_DP || encoder->type == INTEL_OUTPUT_DP_MST || encoder->type == INTEL_OUTPUT_EDP) { - enum intel_dpll_id pll_id; - - switch (clock / 2) { - case 81000: - pll_id = DPLL_ID_LCPLL_810; - break; - case 135000: - pll_id = DPLL_ID_LCPLL_1350; - break; - case 270000: - pll_id = DPLL_ID_LCPLL_2700; - break; - default: - DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); - return NULL; - } - - pll = intel_get_shared_dpll_by_id(dev_priv, pll_id); + pll = hsw_ddi_dp_get_dpll(encoder, clock); } else if (encoder->type == INTEL_OUTPUT_ANALOG) { if (WARN_ON(crtc_state->port_clock / 2 != 135000)) @@ -774,7 +799,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state, return pll; } - static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { .enable = hsw_ddi_wrpll_enable, .disable = hsw_ddi_wrpll_disable, diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index ec0fe66..f438535 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -164,10 +164,16 @@ void intel_shared_dpll_init(struct drm_device *dev); bool bxt_ddi_dp_set_dpll_hw_state(int clock, struct intel_dpll_hw_state *dpll_hw_state); + /* SKL dpll related functions */ bool skl_ddi_dp_set_dpll_hw_state(int clock, struct intel_dpll_hw_state *dpll_hw_state); struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv, int clock); + +/* HSW dpll related functions */ +struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, + int clock); + #endif /* _INTEL_DPLL_MGR_H_ */
Split out the DisplayPort and HDMI pll setup code into separate functions and refactor the DP code that calculates the pll so that it doesn't depend on crtc state. This will be used for acquiring port pll when doing upfront link training. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 90 ++++++++++++++++++++++------------- drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 +++ 2 files changed, 63 insertions(+), 33 deletions(-)