From patchwork Fri Aug 19 23:33:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9291373 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F3210607FF for ; Fri, 19 Aug 2016 23:20:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7981295BA for ; Fri, 19 Aug 2016 23:20:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B84BE295DC; Fri, 19 Aug 2016 23:20:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3621B295BA for ; Fri, 19 Aug 2016 23:20:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0912E6EC93; Fri, 19 Aug 2016 23:20:18 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTP id 940DE6EC93 for ; Fri, 19 Aug 2016 23:20:16 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP; 19 Aug 2016 16:20:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,546,1464678000"; d="scan'208"; a="1017626139" Received: from manasi-otcmedia.jf.intel.com ([10.7.199.175]) by orsmga001.jf.intel.com with ESMTP; 19 Aug 2016 16:20:16 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Fri, 19 Aug 2016 16:33:41 -0700 Message-Id: <1471649629-4091-1-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1470770143-5163-1-git-send-email-manasi.d.navare@intel.com> References: <1470770143-5163-1-git-send-email-manasi.d.navare@intel.com> Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Don't pass crtc_state to intel_dp_set_link_params() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ander Conselvan de Oliveira Decouple intel_dp_set_link_params() from struct intel_crtc_state. This will be useful for implementing DP upfront link training. Reviewed-by: Durgadoss R Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_ddi.c | 5 ++++- drivers/gpu/drm/i915/intel_dp.c | 14 +++++++++----- drivers/gpu/drm/i915/intel_dp_mst.c | 6 ++++-- drivers/gpu/drm/i915/intel_drv.h | 3 ++- 4 files changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c2df4e4..530ee9f 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1637,7 +1637,10 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) intel_prepare_dp_ddi_buffers(intel_encoder); - intel_dp_set_link_params(intel_dp, crtc->config); + intel_dp_set_link_params(intel_dp, crtc->config->port_clock, + crtc->config->lane_count, + intel_crtc_has_type(crtc->config, + INTEL_OUTPUT_DP_MST)); intel_ddi_init_dp_buf_reg(intel_encoder); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 364db90..2cfb2ae 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1640,11 +1640,12 @@ found: } void intel_dp_set_link_params(struct intel_dp *intel_dp, - const struct intel_crtc_state *pipe_config) + int link_rate, uint8_t lane_count, + bool link_mst) { - intel_dp->link_rate = pipe_config->port_clock; - intel_dp->lane_count = pipe_config->lane_count; - intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); + intel_dp->link_rate = link_rate; + intel_dp->lane_count = lane_count; + intel_dp->link_mst = link_mst; } static void intel_dp_prepare(struct intel_encoder *encoder) @@ -1656,7 +1657,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder) struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; - intel_dp_set_link_params(intel_dp, crtc->config); + intel_dp_set_link_params(intel_dp, crtc->config->port_clock, + crtc->config->lane_count, + intel_crtc_has_type(crtc->config, + INTEL_OUTPUT_DP_MST)); /* * There are four kinds of DP registers: diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 629337d..e654fea 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -173,8 +173,10 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) intel_ddi_clk_select(&intel_dig_port->base, intel_crtc->config); intel_prepare_dp_ddi_buffers(&intel_dig_port->base); - - intel_dp_set_link_params(intel_dp, intel_crtc->config); + intel_dp_set_link_params(intel_dp, + intel_crtc->config->port_clock, + intel_crtc->config->lane_count, + true); intel_ddi_init_dp_buf_reg(&intel_dig_port->base); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 774aab3..990a9b9 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1367,7 +1367,8 @@ bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, struct intel_connector *intel_connector); void intel_dp_set_link_params(struct intel_dp *intel_dp, - const struct intel_crtc_state *pipe_config); + int link_rate, uint8_t lane_count, + bool link_mst); void intel_dp_start_link_train(struct intel_dp *intel_dp); void intel_dp_stop_link_train(struct intel_dp *intel_dp); void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);