[7/9] drm/i915/dp: Enable upfront link training on SKL

Commit Message

Navare, Manasi Aug. 19, 2016, 11:33 p.m. UTC

From: Jim Bride <[e-mail]>

Split the PLL selection code out of the BXT upfront link training
implementation and into a stand-alone function in order to allow
for the implementation of a platform neutral upfront link training
function, and then enable upfront link training for Skylake.

Signed-off-by: Jim Bride <[e-mail]>
---
 drivers/gpu/drm/i915/intel_ddi.c      | 56 ++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_dp.c       |  4 +--
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 38 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 ++
 drivers/gpu/drm/i915/intel_drv.h      |  4 ++-
 5 files changed, 84 insertions(+), 20 deletions(-)

Comments

David Weinehall Aug. 20, 2016, 9:52 a.m. UTC | #1

On Fri, Aug 19, 2016 at 04:33:47PM -0700, Manasi Navare wrote:
> From: Jim Bride <[e-mail]>
> 
> Split the PLL selection code out of the BXT upfront link training
> implementation and into a stand-alone function in order to allow
> for the implementation of a platform neutral upfront link training
> function, and then enable upfront link training for Skylake.
> 
> Signed-off-by: Jim Bride <[e-mail]>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c      | 56 ++++++++++++++++++++++++-----------
>  drivers/gpu/drm/i915/intel_dp.c       |  4 +--
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 38 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  2 ++
>  drivers/gpu/drm/i915/intel_drv.h      |  4 ++-
>  5 files changed, 84 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 3921230..ef63b4b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2378,8 +2378,43 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
>  	return connector;
>  }
>  
> +struct intel_shared_dpll *
> +intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
> +{
> +	struct intel_connector *connector = intel_dp->attached_connector;
> +	struct intel_encoder *encoder = connector->encoder;
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_shared_dpll *pll = NULL;
> +	struct intel_shared_dpll_config tmp_pll_config;
> +	enum intel_dpll_id dpll_id;
> +
> +	if (IS_BROXTON(dev_priv)) {
> +		dpll_id =  (enum intel_dpll_id)dig_port->port;
> +		/*
> +		 * Select the required PLL. This works for platforms where
> +		 * there is no shared DPLL.
> +		 */
> +		pll = &dev_priv->shared_dplls[dpll_id];
> +		if (WARN_ON(pll->active_mask)) {
> +
> +			DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
> +				  pll->active_mask);
> +			pll = NULL;
> +		}
> +		tmp_pll_config = pll->config;
> +		if (!bxt_ddi_dp_set_dpll_hw_state(clock,
> +						  &pll->config.hw_state)) {
> +			DRM_ERROR("Could not setup DPLL\n");
> +			pll->config = tmp_pll_config;
> +		}
> +	} else if (IS_SKYLAKE(dev_priv)) {
> +		pll = skl_find_link_pll(dev_priv, clock);
> +	}
> +	return pll;
> +}
>  
> -bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
> +bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp,
>  				  int clock, uint8_t lane_count,
>  				  bool link_mst)
>  {
> @@ -2388,28 +2423,15 @@ bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_shared_dpll *pll;
>  	struct intel_shared_dpll_config tmp_pll_config;
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
>  
> -	/*
> -	 * FIXME: Works only for BXT.
> -	 * Select the required PLL. This works for platforms where
> -	 * there is no shared DPLL.
> -	 */
> -	pll = &dev_priv->shared_dplls[dpll_id];
> -	if (WARN_ON(pll->active_mask)) {
> -		DRM_ERROR("Shared DPLL already in use. active_mask:%x\n", pll->active_mask);
> +	pll = intel_ddi_get_link_dpll(intel_dp, clock);
> +	if (pll == NULL) {
> +		DRM_ERROR("Could not find DPLL for link training.\n");
>  		return false;
>  	}
>  
>  	tmp_pll_config = pll->config;
>  
> -	if (!bxt_ddi_dp_set_dpll_hw_state(clock, &pll->config.hw_state)) {
> -		DRM_ERROR("Could not setup DPLL\n");
> -		pll->config = tmp_pll_config;
> -		return false;
> -	}
> -
>  	/* Enable PLL followed by port */
>  	pll->funcs.enable(dev_priv, pll);
>  	intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll, link_mst);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 5e362eb..fe156fb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5757,8 +5757,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  
>  	/* Initialize upfront link training vfunc for DP */
>  	if (intel_encoder->type != INTEL_OUTPUT_EDP) {
> -		if (IS_BROXTON(dev))
> -			intel_dp->upfront_link_train = intel_bxt_upfront_link_train;
> +		if (IS_BROXTON(dev) || IS_SKYLAKE(dev))

dev_priv, dev_priv

> +			intel_dp->upfront_link_train = intel_ddi_upfront_link_train;
>  	}
>  
>  	/* eDP only on port B and/or C on vlv/chv */
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 8ce220e..e5c025e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -24,6 +24,44 @@
>  #include "intel_drv.h"
>  
>  struct intel_shared_dpll *
> +skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
> +{
> +	struct intel_shared_dpll *pll = NULL;
> +	struct intel_dpll_hw_state dpll_hw_state;
> +	enum intel_dpll_id i;
> +	bool found = false;
> +
> +	if (!skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
> +		return pll;
> +
> +	for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) {
> +		pll = &dev_priv->shared_dplls[i];
> +
> +		/* Only want to check enabled timings first */
> +		if (pll->config.crtc_mask == 0)
> +			continue;
> +
> +		if (memcmp(&dpll_hw_state, &pll->config.hw_state,
> +			   sizeof(pll->config.hw_state)) == 0) {
> +			found = true;
> +			break;
> +		}
> +	}
> +
> +	/* Ok no matching timings, maybe there's a free one? */
> +	for (i = DPLL_ID_SKL_DPLL1;
> +	     ((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) {
> +		pll = &dev_priv->shared_dplls[i];
> +		if (pll->config.crtc_mask == 0) {
> +			pll->config.hw_state = dpll_hw_state;
> +			break;
> +		}
> +	}
> +
> +	return pll;
> +}
> +
> +struct intel_shared_dpll *
>  intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
>  			    enum intel_dpll_id id)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index cb28f8d..ec0fe66 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -167,5 +167,7 @@ bool bxt_ddi_dp_set_dpll_hw_state(int clock,
>  /* SKL dpll related functions */
>  bool skl_ddi_dp_set_dpll_hw_state(int clock,
>  				  struct intel_dpll_hw_state *dpll_hw_state);
> +struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv,
> +					    int clock);
>  
>  #endif /* _INTEL_DPLL_MGR_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8b3d062..374cbbd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1158,9 +1158,11 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>  			 struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
> -bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
> +bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp,
>  				  int clock, uint8_t lane_count,
>  				  bool link_mst);
> +struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
> +						  int clock);
>  
>  unsigned int intel_fb_align_height(struct drm_device *dev,
>  				   unsigned int height,

Patch

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3921230..ef63b4b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2378,8 +2378,43 @@  intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
 	return connector;
 }
 
+struct intel_shared_dpll *
+intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock)
+{
+	struct intel_connector *connector = intel_dp->attached_connector;
+	struct intel_encoder *encoder = connector->encoder;
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct intel_shared_dpll *pll = NULL;
+	struct intel_shared_dpll_config tmp_pll_config;
+	enum intel_dpll_id dpll_id;
+
+	if (IS_BROXTON(dev_priv)) {
+		dpll_id =  (enum intel_dpll_id)dig_port->port;
+		/*
+		 * Select the required PLL. This works for platforms where
+		 * there is no shared DPLL.
+		 */
+		pll = &dev_priv->shared_dplls[dpll_id];
+		if (WARN_ON(pll->active_mask)) {
+
+			DRM_ERROR("Shared DPLL in use. active_mask:%x\n",
+				  pll->active_mask);
+			pll = NULL;
+		}
+		tmp_pll_config = pll->config;
+		if (!bxt_ddi_dp_set_dpll_hw_state(clock,
+						  &pll->config.hw_state)) {
+			DRM_ERROR("Could not setup DPLL\n");
+			pll->config = tmp_pll_config;
+		}
+	} else if (IS_SKYLAKE(dev_priv)) {
+		pll = skl_find_link_pll(dev_priv, clock);
+	}
+	return pll;
+}
 
-bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
+bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp,
 				  int clock, uint8_t lane_count,
 				  bool link_mst)
 {
@@ -2388,28 +2423,15 @@  bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll;
 	struct intel_shared_dpll_config tmp_pll_config;
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port;
 
-	/*
-	 * FIXME: Works only for BXT.
-	 * Select the required PLL. This works for platforms where
-	 * there is no shared DPLL.
-	 */
-	pll = &dev_priv->shared_dplls[dpll_id];
-	if (WARN_ON(pll->active_mask)) {
-		DRM_ERROR("Shared DPLL already in use. active_mask:%x\n", pll->active_mask);
+	pll = intel_ddi_get_link_dpll(intel_dp, clock);
+	if (pll == NULL) {
+		DRM_ERROR("Could not find DPLL for link training.\n");
 		return false;
 	}
 
 	tmp_pll_config = pll->config;
 
-	if (!bxt_ddi_dp_set_dpll_hw_state(clock, &pll->config.hw_state)) {
-		DRM_ERROR("Could not setup DPLL\n");
-		pll->config = tmp_pll_config;
-		return false;
-	}
-
 	/* Enable PLL followed by port */
 	pll->funcs.enable(dev_priv, pll);
 	intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll, link_mst);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e362eb..fe156fb 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5757,8 +5757,8 @@  intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 
 	/* Initialize upfront link training vfunc for DP */
 	if (intel_encoder->type != INTEL_OUTPUT_EDP) {
-		if (IS_BROXTON(dev))
-			intel_dp->upfront_link_train = intel_bxt_upfront_link_train;
+		if (IS_BROXTON(dev) || IS_SKYLAKE(dev))
+			intel_dp->upfront_link_train = intel_ddi_upfront_link_train;
 	}
 
 	/* eDP only on port B and/or C on vlv/chv */
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 8ce220e..e5c025e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -24,6 +24,44 @@ 
 #include "intel_drv.h"
 
 struct intel_shared_dpll *
+skl_find_link_pll(struct drm_i915_private *dev_priv, int clock)
+{
+	struct intel_shared_dpll *pll = NULL;
+	struct intel_dpll_hw_state dpll_hw_state;
+	enum intel_dpll_id i;
+	bool found = false;
+
+	if (!skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
+		return pll;
+
+	for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) {
+		pll = &dev_priv->shared_dplls[i];
+
+		/* Only want to check enabled timings first */
+		if (pll->config.crtc_mask == 0)
+			continue;
+
+		if (memcmp(&dpll_hw_state, &pll->config.hw_state,
+			   sizeof(pll->config.hw_state)) == 0) {
+			found = true;
+			break;
+		}
+	}
+
+	/* Ok no matching timings, maybe there's a free one? */
+	for (i = DPLL_ID_SKL_DPLL1;
+	     ((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) {
+		pll = &dev_priv->shared_dplls[i];
+		if (pll->config.crtc_mask == 0) {
+			pll->config.hw_state = dpll_hw_state;
+			break;
+		}
+	}
+
+	return pll;
+}
+
+struct intel_shared_dpll *
 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
 			    enum intel_dpll_id id)
 {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index cb28f8d..ec0fe66 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -167,5 +167,7 @@  bool bxt_ddi_dp_set_dpll_hw_state(int clock,
 /* SKL dpll related functions */
 bool skl_ddi_dp_set_dpll_hw_state(int clock,
 				  struct intel_dpll_hw_state *dpll_hw_state);
+struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv,
+					    int clock);
 
 #endif /* _INTEL_DPLL_MGR_H_ */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8b3d062..374cbbd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1158,9 +1158,11 @@  void intel_ddi_clock_get(struct intel_encoder *encoder,
 			 struct intel_crtc_state *pipe_config);
 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
-bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp,
+bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp,
 				  int clock, uint8_t lane_count,
 				  bool link_mst);
+struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp,
+						  int clock);
 
 unsigned int intel_fb_align_height(struct drm_device *dev,
 				   unsigned int height,