From patchwork Tue Aug 23 01:41:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Navare, Manasi" X-Patchwork-Id: 9295589 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 78324607D0 for ; Tue, 23 Aug 2016 12:31:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 696462877C for ; Tue, 23 Aug 2016 12:31:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5E70D28792; Tue, 23 Aug 2016 12:31:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C00782877C for ; Tue, 23 Aug 2016 12:31:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF9506E7E9; Tue, 23 Aug 2016 12:29:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id ACC6B6E58B for ; Tue, 23 Aug 2016 01:27:54 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP; 22 Aug 2016 18:27:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,563,1464678000"; d="scan'208"; a="1039927674" Received: from manasi-otcmedia.jf.intel.com ([10.7.199.175]) by orsmga002.jf.intel.com with ESMTP; 22 Aug 2016 18:27:54 -0700 From: Manasi Navare To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Aug 2016 18:41:06 -0700 Message-Id: <1471916468-30588-7-git-send-email-manasi.d.navare@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471916468-30588-1-git-send-email-manasi.d.navare@intel.com> References: <1471916468-30588-1-git-send-email-manasi.d.navare@intel.com> In-Reply-To: <1470770143-5163-1-git-send-email-manasi.d.navare@intel.com> References: <1470770143-5163-1-git-send-email-manasi.d.navare@intel.com> Subject: [Intel-gfx] [PATCH v2 7/9] drm/i915/dp: Enable upfront link training on SKL X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Jim Bride Split the PLL selection code out of the BXT upfront link training implementation and into a stand-alone function in order to allow for the implementation of a platform neutral upfront link training function, and then enable upfront link training for Skylake. v2: * Change the macro to use dev_priv instead of dev (David Weinehall) Reviewed-by: Durgadoss R Signed-off-by: Manasi Navare Signed-off-by: Jim Bride --- drivers/gpu/drm/i915/intel_ddi.c | 56 ++++++++++++++++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 4 +-- drivers/gpu/drm/i915/intel_dpll_mgr.c | 38 ++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_dpll_mgr.h | 2 ++ drivers/gpu/drm/i915/intel_drv.h | 4 ++- 5 files changed, 84 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 3921230..ef63b4b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2378,8 +2378,43 @@ intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) return connector; } +struct intel_shared_dpll * +intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock) +{ + struct intel_connector *connector = intel_dp->attached_connector; + struct intel_encoder *encoder = connector->encoder; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_shared_dpll *pll = NULL; + struct intel_shared_dpll_config tmp_pll_config; + enum intel_dpll_id dpll_id; + + if (IS_BROXTON(dev_priv)) { + dpll_id = (enum intel_dpll_id)dig_port->port; + /* + * Select the required PLL. This works for platforms where + * there is no shared DPLL. + */ + pll = &dev_priv->shared_dplls[dpll_id]; + if (WARN_ON(pll->active_mask)) { + + DRM_ERROR("Shared DPLL in use. active_mask:%x\n", + pll->active_mask); + pll = NULL; + } + tmp_pll_config = pll->config; + if (!bxt_ddi_dp_set_dpll_hw_state(clock, + &pll->config.hw_state)) { + DRM_ERROR("Could not setup DPLL\n"); + pll->config = tmp_pll_config; + } + } else if (IS_SKYLAKE(dev_priv)) { + pll = skl_find_link_pll(dev_priv, clock); + } + return pll; +} -bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp, +bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp, int clock, uint8_t lane_count, bool link_mst) { @@ -2388,28 +2423,15 @@ bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_shared_dpll *pll; struct intel_shared_dpll_config tmp_pll_config; - struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); - enum intel_dpll_id dpll_id = (enum intel_dpll_id)dig_port->port; - /* - * FIXME: Works only for BXT. - * Select the required PLL. This works for platforms where - * there is no shared DPLL. - */ - pll = &dev_priv->shared_dplls[dpll_id]; - if (WARN_ON(pll->active_mask)) { - DRM_ERROR("Shared DPLL already in use. active_mask:%x\n", pll->active_mask); + pll = intel_ddi_get_link_dpll(intel_dp, clock); + if (pll == NULL) { + DRM_ERROR("Could not find DPLL for link training.\n"); return false; } tmp_pll_config = pll->config; - if (!bxt_ddi_dp_set_dpll_hw_state(clock, &pll->config.hw_state)) { - DRM_ERROR("Could not setup DPLL\n"); - pll->config = tmp_pll_config; - return false; - } - /* Enable PLL followed by port */ pll->funcs.enable(dev_priv, pll); intel_ddi_pre_enable_dp(encoder, clock, lane_count, pll, link_mst); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 165d029..e7a67ed 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5757,8 +5757,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, /* Initialize upfront link training vfunc for DP */ if (intel_encoder->type != INTEL_OUTPUT_EDP) { - if (IS_BROXTON(dev_priv)) - intel_dp->upfront_link_train = intel_bxt_upfront_link_train; + if (IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv)) + intel_dp->upfront_link_train = intel_ddi_upfront_link_train; } /* eDP only on port B and/or C on vlv/chv */ diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 8ce220e..e5c025e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -24,6 +24,44 @@ #include "intel_drv.h" struct intel_shared_dpll * +skl_find_link_pll(struct drm_i915_private *dev_priv, int clock) +{ + struct intel_shared_dpll *pll = NULL; + struct intel_dpll_hw_state dpll_hw_state; + enum intel_dpll_id i; + bool found = false; + + if (!skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state)) + return pll; + + for (i = DPLL_ID_SKL_DPLL1; i <= DPLL_ID_SKL_DPLL3; i++) { + pll = &dev_priv->shared_dplls[i]; + + /* Only want to check enabled timings first */ + if (pll->config.crtc_mask == 0) + continue; + + if (memcmp(&dpll_hw_state, &pll->config.hw_state, + sizeof(pll->config.hw_state)) == 0) { + found = true; + break; + } + } + + /* Ok no matching timings, maybe there's a free one? */ + for (i = DPLL_ID_SKL_DPLL1; + ((found == false) && (i <= DPLL_ID_SKL_DPLL3)); i++) { + pll = &dev_priv->shared_dplls[i]; + if (pll->config.crtc_mask == 0) { + pll->config.hw_state = dpll_hw_state; + break; + } + } + + return pll; +} + +struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, enum intel_dpll_id id) { diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index cb28f8d..ec0fe66 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -167,5 +167,7 @@ bool bxt_ddi_dp_set_dpll_hw_state(int clock, /* SKL dpll related functions */ bool skl_ddi_dp_set_dpll_hw_state(int clock, struct intel_dpll_hw_state *dpll_hw_state); +struct intel_shared_dpll *skl_find_link_pll(struct drm_i915_private *dev_priv, + int clock); #endif /* _INTEL_DPLL_MGR_H_ */ diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 3d5f330..55bb39d 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1158,9 +1158,11 @@ void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config); void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); uint32_t ddi_signal_levels(struct intel_dp *intel_dp); -bool intel_bxt_upfront_link_train(struct intel_dp *intel_dp, +bool intel_ddi_upfront_link_train(struct intel_dp *intel_dp, int clock, uint8_t lane_count, bool link_mst); +struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp, + int clock); unsigned int intel_fb_align_height(struct drm_device *dev, unsigned int height,