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[7/7] drm/i915: Pipescaler destination size limit check on Gen9

Message ID 1472533261-30306-8-git-send-email-nabendu.bikash.maiti@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Nabendu Maiti Aug. 30, 2016, 5:01 a.m. UTC 
Pipe scaler on  gen9 destination size may go out of adjusted modeset
size.This patch add limit check on user custom crtc destination size and
clamp it within modeset size.

Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 15d185e..45e5204 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12565,6 +12565,17 @@  intel_gen9_pipe_scale(struct intel_crtc *intel_crtc,
 	    pipe_config->pipe_src_w))
 		goto done;
 
+	/* Out of boundary, clamping it */
+	if ((pipe_config->pipe_dst_x + pipe_config->pipe_dst_w) >
+	     adjusted_mode->hdisplay)
+		pipe_config->pipe_dst_w =
+		(adjusted_mode->hdisplay - pipe_config->pipe_dst_x);
+
+	if ((pipe_config->pipe_dst_y + pipe_config->pipe_dst_h) >
+	    adjusted_mode->vdisplay)
+		pipe_config->pipe_dst_h =
+		(adjusted_mode->vdisplay - pipe_config->pipe_dst_y);
+
 	x = pipe_config->pipe_dst_x;
 	y = pipe_config->pipe_dst_y;
 	width = pipe_config->pipe_dst_w;