From patchwork Mon Sep 19 09:56:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lee, Shawn C" X-Patchwork-Id: 9338905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EF306607D0 for ; Mon, 19 Sep 2016 09:34:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF76728CD5 for ; Mon, 19 Sep 2016 09:34:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D45C028CE8; Mon, 19 Sep 2016 09:34:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E5F228CD5 for ; Mon, 19 Sep 2016 09:34:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 134726E2F7; Mon, 19 Sep 2016 09:34:52 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 57FE06E2F7 for ; Mon, 19 Sep 2016 09:34:45 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP; 19 Sep 2016 02:34:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,361,1470726000"; d="scan'208";a="10741203" Received: from shawnle1-cm6330-cm6630-cm6730-cm6830-m11aa-8.itwn.intel.com ([10.5.230.132]) by fmsmga005.fm.intel.com with ESMTP; 19 Sep 2016 02:34:42 -0700 From: "Lee, Shawn C" To: intel-gfx@lists.freedesktop.org Date: Mon, 19 Sep 2016 17:56:24 +0800 Message-Id: <1474278984-16651-1-git-send-email-shawn.c.lee@intel.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1473329920-4449-1-git-send-email-shawn.c.lee@intel.com> References: <1473329920-4449-1-git-send-email-shawn.c.lee@intel.com> Cc: Jani Nikula Subject: [Intel-gfx] [PATCH] drm/i915 : Restore PWM_GRANULARITY after resume X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: "Lee, Shawn C" SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity (minimum increment) of the PWM backlight control counter. PWM frequency adjustment on 128 clock increments when this bit was 1. And 16 clock increments when it was 0. PWM frequency multiple octuple (from 200Hz to 1.6KHz) due to SPT_PWM_GRANULARITY was clear to 0 after S3. This patch save SOUTH_CHICKEN1 register value before suspend. And will restore it after i915 resume. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97486 Cc: Jani Nikula Reviewed-by: Cooper Chiou Reviewed-by: Wei Shun Chen Reviewed-by: Gary C Wang Signed-off-by: Shawn Lee --- drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_panel.c | 30 ++++++++++++++++++++++++++++-- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 570a7ca..c4bc690 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -256,6 +256,7 @@ struct intel_panel { u32 level; u32 min; u32 max; + bool pwm_alternate_increment; bool enabled; bool combination_mode; /* gen 2/4 only */ bool active_low_pwm; diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index c10e9b0..6f8469b 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -841,7 +841,7 @@ static void lpt_enable_backlight(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; - u32 pch_ctl1, pch_ctl2; + u32 pch_ctl1, pch_ctl2, mul; pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { @@ -867,6 +867,22 @@ static void lpt_enable_backlight(struct intel_connector *connector) /* This won't stick until the above enable. */ intel_panel_actually_set_backlight(connector, panel->backlight.level); + + if (HAS_PCH_LPT(dev_priv)) { + mul = I915_READ(SOUTH_CHICKEN2); + if (panel->backlight.pwm_alternate_increment) + mul |= LPT_PWM_GRANULARITY; + else + mul &= ~LPT_PWM_GRANULARITY; + I915_WRITE(SOUTH_CHICKEN2, mul); + } else { + mul = I915_READ(SOUTH_CHICKEN1); + if (panel->backlight.pwm_alternate_increment) + mul |= SPT_PWM_GRANULARITY; + else + mul &= ~SPT_PWM_GRANULARITY; + I915_WRITE(SOUTH_CHICKEN1, mul); + } } static void pch_enable_backlight(struct intel_connector *connector) @@ -1413,7 +1429,7 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; - u32 pch_ctl1, pch_ctl2, val; + u32 pch_ctl1, pch_ctl2, val, mul; pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; @@ -1436,6 +1452,16 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE; + if (HAS_PCH_LPT(dev_priv)) + mul = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; + else + mul = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; + + if ( mul ) + panel->backlight.pwm_alternate_increment = true; + else + panel->backlight.pwm_alternate_increment = false; + return 0; }