| Message ID | 1475535850-6461-1-git-send-email-jim.bride@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 108ba1e..4d7e2a8 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -199,10 +199,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) if (dev_priv->psr.link_standby) drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); + DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | + DP_PSR_FRAME_CAPTURE); else drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE); + DP_PSR_ENABLE | DP_PSR_FRAME_CAPTURE); aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port);
On some system + panel combinations the vblank interval is too short for PSR setup to occur. While reading the eDP v1.3 spec I saw that Figure 4-7 describes a solution to this very problem by configuring PSR to capture the second active frame after the PSR entry indication in order to provide more time for PSR setup activities. This patch changes our PSR configuration to indicate that the sink should capture the second active frame after PSR entry indication. Cc: jani.nikula@linux.intel.com Cc: ville.syrjala@linux.intel.com Cc: rodrigo.vivi@intel.com Signed-off-by: Jim Bride <jim.bride@linux.intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)